A thermal-driven test application scheme for pre-bond and post-bond scan testing of three-dimensional ICs

Abstract

The three-dimensional (3-D) technology offers a new solution to the increasing density of integrated circuits (ICs). In this work, we propose novel scan architectures for 3-D IC pre-bond and post-bond testing by considering the interconnection overhead of through-silicon-vias (TSVs). Since hotspots in 3-D ICs often cause performance and reliability issues, we also develop different test ordering schemes for prebond and postbond testing to avoid applying test vectors that could worsen the temperature distribution. Experimental results show that the peak temperature can be lowered by 20% with the 3-D scan tree architecture. When combined with the test ordering scheme, the 3-D scan tree can further reduce peak temperature by over 30%. ACM Reference Format:Dong Xiang and Kele Shen. 2014. A thermal-driven test application scheme for pre-bond and post-bond scan testing of three-dimensional ICs.

Simulation Algorithms With Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks

“…Lowering supply voltages, increasing current densities as well as tight design margins demand more accurate large-scale PDN simulation. Advanced technologies [15], [16], three dimensional (3D) IC structures [17]- [19], and increasing complexities of system designs all make VLSI PDNs extremely huge and the simulation tasks time-consuming and computationally challenging. Due to the enormous size of modern designs and long simulation runtime of many cycles, instead of general nonlinear circuit simulation [20], [21], PDN is often modeled as a large-scale linear circuit with voltage supplies and time-varying current sources [22]- [24].…”