Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill

Xiang, Dong; Shen, Kele; Bhattacharya, Bhargab B.; Wen, Xiaoqing; Lin, Xijiang

doi:10.1109/tcad.2015.2474365

Cited by 24 publications

(6 citation statements)

References 39 publications

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“…Another approach known as scan partitioning splits the scan chain into multiple partitions and activates only one partition at any time interval [3,[19][20][21][22][23][24][25]. The partitioning scheme in [19] limits the scan chain transitions from propagating to combinational logic during shifting by activating only one scan path at any time interval.…”

Section: Overview Of Hardware-based Test Power Reduction Approachesmentioning

confidence: 99%

“…A segment regrouping algorithm has been proposed by Yamato et al in [23] which identifies an optimal combination of scan segments to be clocked simultaneously and results in further instantaneous shift power reduction in the scan chain. Methods in [24,25] employ a scan chain grouping technique where only a single scan chain in each group is activated at any time during shift-in and shift-out cycles, and all other scan chains are disabled. Thus, repeated shift-in (shift-out) cycles are required to load the test data (or to shift-out the response data).…”

Section: Overview Of Hardware-based Test Power Reduction Approachesmentioning

confidence: 99%

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The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology

Naeini

Dass²,

Ooi

2017

JLPEA

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Abstract:Excessive power consumption during test application time has severely negative effects on chip reliability since it has an inevitable role in hot spots that appear, degradation of performance, circuit premature destruction, and functional failures. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption in the scan chain but also introduce spurious switching activities in the combinational logic. In this work, a new low power gating scan cell for scan based designs has been proposed in order to reduce power consumption in the scan chain as well as the combinational part during shifting. We have modified the conventional scan cell and augmented it with state preserving and gating logic that enables an average power reduction in combinational logic during shift mode. The new scan cell mitigates the number of transitions during shift and capture cycles. Thus, it reduces the average power consumption inside the scan cell and as a result the scan chain during scan shifting with a low impact on peak power during the capture cycle. Furthermore, due to introducing a new shorter shift path, improvements are observed in terms of propagation delay and power consumption in the scan chain during shifting. This leads to higher feasible shift frequency whereby the shift frequency is limited by the maximum power budget and hence results in reducing the test application time. The post-layout spice simulation results show a 7.21% reduction in total power consumption, an average 12.25% reduction of shift power consumption, and a 50.7% improvement in the clock (CLK)-to-shift propagation delay over the conventional scan cell in Synopsys 32/28 nm standard CMOS technology.

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Section: Overview Of Hardware-based Test Power Reduction Approachesmentioning

confidence: 99%

Section: Overview Of Hardware-based Test Power Reduction Approachesmentioning

confidence: 99%

The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology

Naeini

Dass²,

Ooi

2017

JLPEA

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“…Before truncation, a test generation procedure may achieve complete or close-to-complete fault coverage for the fault model(s) of interest. However, the number of tests in the test set may be excessive even if test compaction is used [20]- [23]. It is then necessary to truncate the test set.…”

Section: Introductionmentioning

confidence: 99%

Increasing the Fault Coverage of a Truncated Test Set

Pomeranz

2022

ACM Trans. Des. Autom. Electron. Syst.

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Defect-aware, cell-aware and gate-exhaustive faults are described by input patterns of subcircuits or cells that are expected to activate defects. Even with single-cycle faults, an n -input subcircuit can have up to 2 n faults with unique fault detection conditions, resulting in a large test set. Such a test set may have to be truncated to fit in the tester memory or satisfy constraints on test application time. In this case, a loss of fault coverage is inevitable. This article considers the test set denoted by T 1 obtained after truncating a larger test set denoted by T 0 . Suppose that the truncation reduces the set of detected faults from the set denoted by D 0 to the set denoted by D 1 . The procedure described in this article modifies the tests in T 1 to gain the detection of faults from D 0 ∖ D 1 , even at the cost of losing the detection of faults from D 1 . The goal is to reduce the fault coverage loss by computing a test set denoted by T 2 that detects a set of faults denoted by D 2 such that | T 2 | = | T 1 | and | D 2 | > | D 1 |. Experimental results for benchmark circuits demonstrate the ability of the procedure to increase the coverage of gate-exhaustive faults over several iterations.

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“…These TSV defects will ultimately lead to the deterioration of the electrical performance of TSVs; they can cause additional signal delays or voltage drops [10]. Consequently, the reliability of 3D-IC can be degraded by the latent defects in TSVs due to the thermal stress [11]. It clearly results in a decrease of the yield and performance of 3D-ICs.…”

Section: Introductionmentioning

confidence: 99%

A low-cost concurrent TSV test architecture with lossless test output compression scheme

et al. 2019

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As the traditional IC design migrates to three-dimensional integrated circuits (3D-ICs) design, new challenges need to be considered carefully to solve its reliability and yield issues. 3D-ICs using through-silicon-vias (TSVs) can have latent defects such as resistive open and bridge defects, which are caused by the thermal stress during the fabrication process. These latent defects lead to the deterioration of the electrical performance of TSVs caused by an undesired increase in the resistance-capacitance (RC) delay. For this reason, various post-bond test methodologies have been studied to improve the reliability of 3D-ICs. Cost reduction in these TSV test architectures is also currently being studied by decreasing various factors such as hardware overhead, test time, and the peak current consumption. Usually, a single test-clock-period is required to determine whether the test result contains the defective TSV. When the test result of any TSVs fails, we use another single test-clock-period to classify its defect type. In this paper, we propose a new TSV test architecture to transfer the combined test output of the test result and the specific defect type to the pad during the single test-clock-period. Our proposed test architecture also provides a reliable block-based concurrent testing to optimize the test time by dividing the die into concurrent blocks. The experimental results showed that our proposed test architecture could reduce the test time and the hardware overhead substantially by ensuring that the reasonable peak power consumption for mass production was reasonable without the test quality being adversely affected.

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Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill

Cited by 24 publications

References 39 publications

The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology

The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology

Increasing the Fault Coverage of a Truncated Test Set

A low-cost concurrent TSV test architecture with lossless test output compression scheme

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