Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors

Snoeij, M.F.; Theuwissen, Albert; Makinwa, Kofi A. A.; Huijsing, Johan H.

doi:10.1109/jssc.2007.908720

Cited by 129 publications

(64 citation statements)

References 12 publications

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“…Therefore, the conversion time of two-step SS-ADC is theoretically 16 times faster than that of the conventional SS-ADC. Two-step SS-ADC is suitable for high speed CIS systems [3][4][5][6][7][8]. Fig.…”

Section: Circuit Descriptionmentioning

confidence: 99%

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Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC

Hwang¹,

Song²

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA (320 x 240) resolution. The fabricated chip size is 5 mm x 3 mm, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.

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Section: Circuit Descriptionmentioning

confidence: 99%

“…Among many kinds of column parallel ADCs, SingleSlope ADC (SS-ADC) is mostly adopted at each column of CIS due to its small chip area and low power consumption [1][2][3][4][5][6]. However, since the conversion speed of SS-ADC is very slow, the frame rate of CIS is also very low.…”

Section: Introductionmentioning

confidence: 99%

Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC

Hwang¹,

Song²

2014

JSTS:Journal of Semiconductor Technology and Science

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“…An additional method of increasing conversion speed has been suggested by using a new column-parallel ADC architecture based on a multiple-ramp single-slope (MRSS) ADC [3,4] which improves upon the techniques in [2]. Further increases in conversion speed can be made by combining the MRSS ADC architecture with the concept of exploiting the amplitude-dependent characteristic of photo shot noise present in image signals [1].…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, there is tradeoff between the increased speed obtained by using a large number of ramps and increased power dissipation of using many ramp buffers. Two-step single-slope ADCs based on multiple ramp signals have been reported in [2] and [4]. However, these twostep single-slope ADCs require several ramp generators corresponding to the number of coarse ADC steps.…”

Section: Introductionmentioning

confidence: 99%

Integration of a New Column-Parallel ADC Technology on CMOS Image Sensor

Nelson

2010

2010 IEEE Workshop on Microelectronics and Electron Devices

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Abstract-A new analog-to-digital converter (ADC) technology called Single-slope look ahead ramp (SSLAR) analog-to-digital converter (ADC) was proposed for column-parallel CMOS image sensors. Additionally, a corresponding programmable ramp generator for SSLAR ADC was also designed in such a way that it only allows flexible code hopping (between 0 and 127 least significant bit (LSB)), code fall back and look-ahead operations in column-parallel ramp ADC. This new ADC technology is able to provide conversion speed improvement depending on individual image information with less than 1.0% image quality degradation. Simulation demonstrated that the conversion speed of this new ADC technology is 4-5x higher than a traditional single-slope ADC with minimal circuitry for processing 8-bit standard gray images as well as 3-4x for standard CIF videos. For processing higher resolution images, the conversion speed may further increase. A prototype chip using the 8-bit SSLAR ADC architecture was realized in a 0.5μm, 2P3M, CMOS process with a layout area of 8.2mm2 .

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“…This type of ADC is commonly used in the areas of CMOS image sensors, radiation sensors, and so on [1,2,3,4]. A single-slope ADC has an advantage of its simplest implementation with minimal analog contents and can provide higher ADC resolution and linearity with the cost of the conversion time.…”

mentioning

confidence: 99%

All-digital ramp waveform generator for two-step single-slope ADC

Iizuka

Asada

2011

IEICE Electron. Express

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This paper presents an all-digital on-chip ramp waveform generator for an 8-bit single-slope ADC. The proposed ramp waveform generator consists of static CMOS digital circuits and is designed using standard cells aiming for the process portability. The proposed circuit realizes digitally-controlled ramp output and also realizes two step coarse-fine ramp waveform to speed up the single-slope analog-todigital conversion. The experimental results of the circuit simulation with random variation on 0.18 μm CMOS process demonstrate the feasibility of our ramp waveform generator and 8-bit two-step single-slope ADC with DNL within ±0.2LSB and INL within ±0.8LSB.

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Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors

Cited by 129 publications

References 12 publications

Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC

Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC

Integration of a New Column-Parallel ADC Technology on CMOS Image Sensor

All-digital ramp waveform generator for two-step single-slope ADC

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