Multiple-image-depth modeling for hotspot and AF printing detections

Tang, Y. P.; Chou, C. S.; Huang, Wen‐Shih; Liu, R. G.; Gau, Tsai‐Sheng

doi:10.1117/12.917402

Cited by 10 publications

(7 citation statements)

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“…Note that different emphases can be made through changing the assumptions of Eqs. (3)- (5). For example, we can focus on the reaction kinetics by designedly assuming that k q is large but finite in Eqs.…”

Section: Assumptions and Approximations In Pebmentioning

confidence: 99%

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Resist profile simulation with fast lithography model

Chou

Tang

et al. 2014

SPIE Proceedings

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A traditional approach to construct a fast lithographic model is to match wafer top-down SEM images, contours and/or gauge CDs with a TCC model plus some simple resist representation. This modeling method has been proven and is extensively used for OPC modeling. As the technology moves forward, this traditional approach has become insufficient in regard to lithography weak point detection, etching bias prediction, etc. The drawback of this approach is from metrology and simulation. First, top-down SEM is only good for acquiring planar CD information. Some 3D metrology such as cross-section SEM or AFM is necessary to obtain the true resist profile. Second, the TCC modeling approach is only suitable for planar image simulation. In order to model the resist profile, full 3D image simulation is needed. Even though there are many rigorous simulators capable of catching the resist profile very well, none of them is feasible for full-chip application due to the tremendous consumption of computational resource. The authors have proposed a quasi-3D image simulation method in the previous study [1], which is suitable for full-chip simulation with the consideration of sidewall angles, to improve the model accuracy of planar models.In this paper, the quasi-3D image simulation is extended to directly model the resist profile with AFM and/or cross-section SEM data. Resist weak points detected by the model generated with this 3D approach are verified on the wafer.

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Section: Assumptions and Approximations In Pebmentioning

confidence: 99%

“…The authors have proposed a method of multi-depth modeling for the detection of hotspot and assistant feature printing [5]. In that work, the authors used 3 separate resist models with aligned optical settings to describe nominal CD, AF printing, and bottom necking respectively.…”

mentioning

confidence: 99%

Resist profile simulation with fast lithography model

Chou

Tang

et al. 2014

SPIE Proceedings

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“…In our previous study, we have proposed a method of multi-depth modeling for the detection of hotspot and assistant feature printing [3]. In that work, acid diffusion through the depth of the photoresist was not considered.…”

Section: Introductionmentioning

confidence: 99%

Joint calibration of 3D resist image and CDSEM

Chou

Tang

et al. 2013

SPIE Proceedings

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Traditionally, an optical proximity correction model is to evaluate the resist image at a specific depth within the photoresist and then extract the resist contours from the image. Calibration is generally implemented by comparing resist contours with the critical dimensions (CD). The wafer CD is usually collected by a scanning electron microscope (SEM), which evaluates the CD based on some criterion that is a function of gray level, differential signal, threshold or other parameters set by the SEM. However, the criterion does not reveal which depth the CD is obtained at. This depth inconsistency between modeling and SEM makes the model calibration difficult for low k 1 images.In this paper, the vertical resist profile is obtained by modifying the model from planar (2D) to quasi-3D approach and comparing the CD from this new model with SEM CD. For this quasi-3D model, the photoresist diffusion along the depth of the resist is considered and the 3D photoresist contours are evaluated. The performance of this new model is studied and is better than the 2D model.

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“…1 To secure a process margin, device manufacturers introduce ultrahighresolution exposure techniques such as optical proximity correction (OPC) and source mask co-optimization. [2][3][4][5][6] Higher degree of integration due to such miniaturization made it possible to realize smaller, faster devices with lower power consumption. In manufacturing processes, film deposition exposure, development, and other operations are performed repeatedly as layers are stacked, and one must manage pattern alignment among layers (overlay) in order to achieve high yield.…”

Section: Introductionmentioning

confidence: 99%

Automatic extraction technique of CD‐SEM evaluation points to measure semiconductor overlay error

Miyamoto

Kawahara

2019

Elect Comm in Japan

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In semiconductor device manufacturing process, it is necessary to measure overlay error between integrated layers. As semiconductor process design rules continue to shrink, small overlay error comes to lead to the fatal fault of the device electrical property. As a result, the needs for the dense overlay measurement in the chip with the use of circuit pattern increase. We propose an automatic extraction technique of the evaluation points (EPs) that are suitable for the overlay measurement by scanning electron microscopy using design data of the device pattern layout. The proposed algorithm extracts all measureable patterns by evaluation of the positional relationship between a segment pair on the upper and lower layers by plural selection indices. Simulation was performed to estimate the overlay error distribution within the shot area using the EPs automatically extracted by the proposed method. The standard deviations of estimation errors in the x-and y-directions were 0.06 nm and 0.10 nm (3ó), respectively. It was confirmed that distortion in the exposure apparatus can be estimated automatically and highly accurately. K E Y W O R D Sautomation, design data, overlay measurement, scanning electron microscope (SEM) 36

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Multiple-image-depth modeling for hotspot and AF printing detections

Cited by 10 publications

References 0 publications

Resist profile simulation with fast lithography model

Resist profile simulation with fast lithography model

Joint calibration of 3D resist image and CDSEM

Automatic extraction technique of CD‐SEM evaluation points to measure semiconductor overlay error

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