Joint calibration of 3D resist image and CDSEM

Abstract

Traditionally, an optical proximity correction model is to evaluate the resist image at a specific depth within the photoresist and then extract the resist contours from the image. Calibration is generally implemented by comparing resist contours with the critical dimensions (CD). The wafer CD is usually collected by a scanning electron microscope (SEM), which evaluates the CD based on some criterion that is a function of gray level, differential signal, threshold or other parameters set by the SEM. However, the criterion does not reveal which depth the CD is obtained at. This depth inconsistency between modeling and SEM makes the model calibration difficult for low k 1 images.In this paper, the vertical resist profile is obtained by modifying the model from planar (2D) to quasi-3D approach and comparing the CD from this new model with SEM CD. For this quasi-3D model, the photoresist diffusion along the depth of the resist is considered and the 3D photoresist contours are evaluated. The performance of this new model is studied and is better than the 2D model.

Resist profile simulation with fast lithography model

“…The authors adopted the quasi-3D resist model approach to obtain the resist sidewall angle and to mitigate the wafer-to-model errors [1]. Samy et al demonstrated a rigorous resist model calibration and the verification with top-down CD SEM, AFM and cross-section SEM [7].…”

“…Even though there are many rigorous simulators capable of catching the resist profile very well, none of them is feasible for full-chip application due to the tremendous consumption of computational resource. The authors have proposed a quasi-3D image simulation method in the previous study [1], which is suitable for full-chip simulation with the consideration of sidewall angles, to improve the model accuracy of planar models.In this paper, the quasi-3D image simulation is extended to directly model the resist profile with AFM and/or cross-section SEM data. Resist weak points detected by the model generated with this 3D approach are verified on the wafer.…”

“…Even though there are many rigorous simulators capable of catching the resist profile very well, none of them is feasible for full-chip application due to the tremendous consumption of computational resource. The authors have proposed a quasi-3D image simulation method in the previous study [1], which is suitable for full-chip simulation with the consideration of sidewall angles, to improve the model accuracy of planar models.…”