Multiple fault analysis using a fault dropping technique

Verreault, Alain; Aboulhamid, E.M.; Karkouri, Y.

doi:10.1109/ftcs.1991.146656

Cited by 8 publications

(3 citation statements)

References 7 publications

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“…We do not have to consider that all inputs of an AND gate are simultaneously s-a-1, because we assume a s-a-1 fault on its output. The resulting procedure from our collapsing is the following [12]:…”

Section: A Fault Collapsingmentioning

confidence: 99%

Use of fault dropping for multiple fault analysis

Karkouri

Aboulhamid²,

Cerny

et al. 1994

IEEE Trans. Comput.

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A new approach to fault analysis is presented. We consider multiple stuck-at-0/1 faults at the gate level. First, a fault collapsing phase is applied to the network, so that equivalent faults are eliminated. During the analysis we consider frontier faults where there is at least a normal path from each faulty line to a primary output. It is shown that the set of frontier faults is equivalent to the set of multiple faults. Given an input vector, we evaluate the fault free circuit and then propagate fault effects. Assuming that fault free response is observed, a fault dropping procedure is then applied to eliminate faulty conditions on lines, that are either absent or may be hidden by other faulty conditions. This method is applied to some benchmark circuits and achieves high degree of efficiency.

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Section: A Fault Collapsingmentioning

confidence: 99%

Use of fault dropping for multiple fault analysis

Karkouri

Aboulhamid²,

Cerny

et al. 1994

IEEE Trans. Comput.

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“…A lot of effort has been made for developing methods to analyze MSAF detection capability in circuits for a given test set, either explicitly [1] or implicitly [2]. In some works, structural constraints and masking relations of single faults are exploited to analyze the detectability of multiple faults [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

Synthesis of multiple fault oriented test groups from single fault test sets

Ubar

Kostin

Raik

2013

2013 8th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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A novel approach for testing and diagnosing of multiple faults is discussed. A definition of a test group is introdueed to eope with the problem of fault masking. The eonditions are introduced to prove that a test group is sufficient to avoid fault masking. A method is presented for generating test groups regarding fault masking. Unlike the traditional test approaches, we do not target the faults as test objectives. The goal is to verify the correctness of a part of the circuit. The whole test sequence is presented as a set of test groups where each group has the goal to identify the correctness of a selected part of a circuit. The method facilitates fault diagnosis in the presence of multiple faults. Experimental research investigates the feasibility of the method and shows a way for tradeoffs between the test cost and robustness of the test regarding multiple faults.

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“…The proposed method is applied to benchmark circuits having double faults, triple faults, and fourfold faults. Experimental results show that suspected faults are identifiedwithin 8 to 30 percent of all stuck-at 0 and 1 faults on all lines in the circuit.…”

Section: Introductionmentioning

confidence: 99%

Multiple fault diagnosis in combinational circuits using sensitizing input‐pairs

Yanagida

Takahashi

Takamatsu

1995

Systems & Computers in Japan

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This paper presents a new method for multiple fault diagnosis of combinational circuits using sensitizing input‐pairs. A partition of a circuit under test into subtree circuits and a generation method for diagnostic test are described. The set of diagnostic tests used in this paper is one of sensitizing input‐pairs that generate sensitizing paths including checkpoints on them. By studying the relation between a sensitizing path generated by a sensitizing input‐pair and a subtree circuit, a method is presented for multiple fault diagnosis in the subtree circuit based on the fault‐free and the faulty responses observed at primary outputs. A deduction algorithm is described for a value at an output of a subtree circuit which does not have a primary output. The proposed method is applied to benchmark circuits having double faults, triple faults, and fourfold faults. Experimental results show that suspected faults are identified within 8 to 30 percent of all stuck‐at 0 and 1 faults on all lines in the circuit.

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Multiple fault analysis using a fault dropping technique

Cited by 8 publications

References 7 publications

Use of fault dropping for multiple fault analysis

Use of fault dropping for multiple fault analysis

Synthesis of multiple fault oriented test groups from single fault test sets

Multiple fault diagnosis in combinational circuits using sensitizing input‐pairs

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