Multilayer Si shadow mask processing of wafer-scale MoS₂ devices

Abstract

Two-dimensional layered materials (2DLMs) have attracted great research interest due to their exotic physical properties and potential applications in nanoelectronics and optoelectronics. Device fabrication with 2DLMs is challenging because their ultrathin characteristic makes them extremely sensitive to the external environment, especially to chemical contamination introduced by optical lithography. The shadow mask technique is a clean alternative in lithography-free electrode patterning for emerging nanomaterials. However, shadow mask assisted fabrication over large areas and multilevel alignment of patterns remain challenging for practical applications. In this paper, we report an over wafer scale shadow mask fabrication technique for 2DLMs. Based on successful fabrication of customized silicon shadow masks with micrometer feature sizes, their advantages for fabricating higher mobility and lower interface trapped exfoliated MoS 2 transistors are demonstrated. Meanwhile, applications in large-scale metal deposition and sample etching are also explored. The max alignment error of multilayer patterns fall in 0.5-3.0 µm in x-and 2.0-9.0 µm in y -directions. Then this technique is employed to realize a fabrication of MoS 2 top-gated field effect transistor arrays with two universal strategies: 'etching-last' and 'channel-first' on 1 × 1 cm 2 Al 2 O 3 substrate. Furthermore, logic inverter circuits with a high gain of 10 are successfully fabricated. The results provide an alternative as a universal, low-cost, time-saving method for fabricating large-scale 2DLM electronics and flexible electronics.

Progress in Epitaxial Thin‐Film Na3Bi as a Topological Electronic Material

“…Aspects of these challenges are being addressed by the development of different stencil mask materials to achieve nanometer‐scale patterning resolution for a wide variety of applications. [ 182 ] Patterned Si 3 N 4 membranes can achieve 15 nm feature size, [ 182 ] while silicon‐wafer based masks have achieved wafer‐scale size for the patterning of 2D materials, [ 183 ] two promising avenues for future exploration.…”

Double shadow masking sample preparation method for in‐situ TEM characterization

“…Shadow masking methods contain several advantages such as reusability, low cost, high precision at the sub-micron scale [22,23] and allows for simple reproduction of electronic devices, nanostructures and multilayers. [20,24,25] Figure 1A-D shows the graphical illustration of the proposed double masking technique for TEM-Window. The typical dimensions of the commercial electron transparent window squared window are given by the edge length between 60 to 100 μm with typically 9 sample spots as shown in Figure 1A.…”

“…Shadow masking methods contain several advantages such as reusability, low cost, high precision at the sub‐micron scale [ 22,23 ] and allows for simple reproduction of electronic devices, nanostructures and multilayers. [ 20,24,25 ]…”

High‐Resolution Van der Waals Stencil Lithography for 2D Transistors

“…Considerable efforts have been devoted to develop new lithography process that is compatible with delicate 2D lattice, to improve the contact and overall device performance. Early attempts utilize rigid shadow masks to avoid the conventional lithography process, [14][15][16] enabling high performance MoS 2 transistor with four-terminal mobility over 480 cm 2 V −1 s −1 on a polymethyl methacrylate (PMMA) substrate. [17] However, due to inherent gap between mask and the substrate, significant blurring of the deposited electrodes is observed, [18,19] limiting the lithography resolution and alignment accuracy for nanoscaled devices.…”