High‐Resolution Van der Waals Stencil Lithography for 2D Transistors

Abstract

2D semiconductors have attracted tremendous attention as an atomically thin channel for transistors with superior immunity to short‐channel effects. However, with atomic thin structure, the delicate 2D lattice is not fully compatible with conventional lithography processes that typically involve high‐energy photon/electron radiation and unavoidable polymer residues, posing a key limitation for high performance 2D transistors. Here, a novel van der Waals (vdW) stencil lithography technique based on dry mask lamination process is developed. By pre‐fabricating polymethyl methacrylate (PMMA) resist with designed patterns, the whole PMMA mask layers could be mechanically released from the sacrifice wafer and physically laminated on top of various 2D semiconductors. The vdW stencil lithography ensures pristine 2D surface without any high‐energy electron/photon radiation, polymer residues, or chemical doping effects in conventional lithography process; and the soft nature of PMMA enables intimate contact between the mask and the 2D materials without physical gap, leading to ultra‐high resolution down to 60 nm. Together, by applying vdW stencil lithography for 2D semiconductors, high performance transistors are demonstrated. Our method not only demonstrates improved 2D transistor performance without lithography induced damages, but also provides a new vdW stencil lithography technique for 2D materials with high resolution.

Strain Releasing of Flexible 2D Electronics through van der Waals Sliding Contact

“…To fabricate the control device with evaporated contact, graphene is first mechanically exfoliated onto the PDMS stamp from bulk crystal and then transferred on the PI substrate. Next, the PMMA soft mask 61 is dry-transferred on the graphene surface. Last, Au (50 nm thick) is deposited through thermal evaporation under vacuum (pressure ∼10 −4 Pa, Supplementary Figure 1e−h).…”

Wafer-scale and universal van der Waals metal semiconductor contact

“…We note that the steel-based stencil mask is used in our process, which typically have a resolution >10 μm. This resolution could be further improved to sub-μm using polymer-based stencil mask 53 .…”

Nanobridge Stencil Enabling High Resolution Arbitrarily Shaped Metallic Thin Films on Various Substrates

“…[13] In addition, SL was used to fabricate electrical contacts on 2D materials for its documented lower impact on the material properties when compared to electron beam lithography (EBL). [14] Rigid, and chemically resistant stencils are commonly fabricated using silicon nitride (SiN) as membrane material. SiN is broadly used in semiconductor processes because it can be grown by chemical vapor deposition (CVD).…”