Multichannel, Low Nonlinearity Time-to-Digital Converters Based on 20 and 28 nm FPGAs

Abstract

This paper presents low nonlinearity, compact, and multichannel time-to-digital converters (TDC) in Xilinx 28 nm Virtex 7 and 20 nm UltraScale field-programmable gate arrays (FPGAs). The proposed TDCs integrate several innovative methods that we have developed: 1) the subtapped delay line averaging topology; 2) tap timing tests; 3) a direct compensation architecture; and 4) a mixed calibration method. The code density tests show that the proposed TDCs have much better linearity performances than previously reported ones. Our approach is cost-effective in terms of the consumption of logic resources. To demonstrate this, we implemented 96 channel TDCs in both FPGAs, using less than 25% of the logic resources. The achieved least significant bit (LSB) is 10.5 ps for Virtex 7 and 5.0 ps for UltraScale FPGAs. After the compensation and calibration, the differential nonlinearity (DNL) is within [-0.05, 0.08] LSB with σDNL = 0.01 LSB, and the integral nonlinearity (INL) is within [-0.09, 0.11] LSB with σINL = 0.04 LSB for the Virtex 7 FPGA. The DNL is within [-0.12, 0.11] LSB with σDNL = 0.03 LSB, and the INL is within [-0.15, 0.48] LSB with σINL = 0.20 LSB for the UltraScale FPGA. Index Terms-Carry chains, field-programmable gate arrays (FPGA), multichannel TDCs, time-of-flight, time-todigital converters (TDC).

Fine resolution delay tuning method to improve the linearity of an unbalanced time‐to‐digital converter on a Xilinx FPGA

“…TDCs reported in [12, 27], based, respectively, on averaging multiple tapped delay lines (TDLs) and a run‐time calibration scheme, also achieved a DNL and INL below the proposed ones in this paper. The TDC in [28] shows the best linearity performances as it integrates several innovative methods such as the delay line averaging methodology, a compensation architecture and a mixed calibration method. It was also implemented in a newer process‐technology FPGA.…”

Multichannel Ring Oscillator Based Time Interval Measurement with Binwidth Calibration

“…A missing code free TDC with low nonlinearity error is suggested with direct calibration bin-width technique [4]. In this approach, vernier delay lines were proposed as it represents improved presentation on comparing the tapped delay lines tuned.…”

“…There are many TDC architectures that are proposed and implemented which give different precisions and time intervals. The multichannel low nonlinearity TDC [4] is proposed which integrates several innovative methods for a better linearity performance. The MUX based encoder [5] in TDC is used for precise measurements.…”

128-Channel High-Linearity Resolution-Adjustable Time-to-Digital Converters for LiDAR Applications: Software Predictions and Hardware Implementations

“…Won and Lee reported that the TDL could be tuned by changing carry-chain modules' output patterns, resulting in better linearity [25]. In 2019, we proposed a mixed-calibration (MC) method [26] showing a 5.0 ps high-linearity FPGA-TDC (DNL − = 0.27 LSB and INL − = 0.51 LSB), comparable to ASIC-TDCs with a similar resolution [27], [28] (R2, Minor 1; R3, Major 1).…”