Multi-$V_{T}$ UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

Noël, J.‐P.; Thomas, Olivier; Jaud, M.-A.; Weber, O.; Poiroux, T.; Fenouillet-Béranger, C.; Rivallin, P.; Scheiblin, P.; Andrieu, F.; Vinet, M.; Rozeau, O.; Bœuf, F.; Faynot, O.; Amara, Ayed Ben

doi:10.1109/ted.2011.2155658

Cited by 168 publications

(54 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Different voltage can be applied independently at the top and at the buried gate [15], and dependently change the Figure 8. Leakage current w.r.t silicon thickness [13].…”

Section: -Nm Utbb Fd-soimentioning

confidence: 99%

28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part I

Mohsen¹,

Harb²,

Deltimple³

et al. 2017

View full text Add to dashboard Cite

Nowadays, transistor technology is going toward the fully depleted architecture; the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performance especially at the node 28 nm. This is the first of two papers that discuss the basic drawbacks of the bulk transistors and explain the two alternative transistors: 28 nm UTBB FD-SOI CMOS and the 22 nm Tri-Gate FinFET. The accompanying paper, Part II, focuses on the comparison between those alternatives and their physical properties, electrical properties, and reliability tests to properly set the preferences when choosing for different mobile media and consumers' applications.

show abstract

“…Different voltage can be applied independently at the top and at the buried gate [15], and dependently change the Figure 8. Leakage current w.r.t silicon thickness [13].…”

Section: -Nm Utbb Fd-soimentioning

confidence: 99%

28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part I

Mohsen¹,

Harb²,

Deltimple³

et al. 2017

View full text Add to dashboard Cite

show abstract

“…V B0 mainly depends on the back-plane work function (typically from 4.1eV to 5.1eV). The importance of the back-face effect depends on the body factor, which can be described as the capacitance ratio between back and front faces [Noel et al 2011]. The body factor for both n-and p-type achieves more than 85mV/V , which is equivalent to bulk technology.…”

Section: Ultra-wide-voltage-range Design Through Additional Electrostmentioning

confidence: 99%

“…Effectively, UTBB FDSOI is able to span a large set of operating points ranging from high performance to low power [Beigné et al 2013], thereby bringing a new offer for dynamic tuning of performance. A dynamic tuning of performance is of interest for a large range of design targets, ranging from logic gates [Noel et al 2011] to embedded memories [Thomas et al 2012]. Such techniques were recently employed in a low-power digital signal processing (DSP) design [Wilson et al 2014], demonstrating the large interest in the approach.…”

Section: Ultra-wide-voltage-range Design Through Additional Electrostmentioning

confidence: 99%

A Survey on Low-Power Techniques with Emerging Technologies

Gaillardon

Beigné

Lesecq

et al. 2015

J. Emerg. Technol. Comput. Syst.

View full text Add to dashboard Cite

Nowadays, power consumption is one of the main limitations of electronic systems. In this context, novel and emerging devices provide new opportunities to extend the trend toward low-power design. In this survey article, we present a transversal survey on energy-efficient techniques ranging from devices to architectures. The actual trends of device research, with fully depleted planar devices, tri-gate geometries, and gateall-around structures, allows us to reach an increasingly higher level of performance while reducing the associated power. In addition, beyond the simple device property enhancements, emerging devices also lead to innovations at the circuit and architectural levels. In particular, devices whose properties can be tuned through additional terminals enable a fine and dynamic control of device threshold. They also enable designers to realize logic gates and to implement power-related techniques in a compact way unreachable to standard technologies. These innovations reduce power consumption at the gate level and unlock new means of actuation in architectural solutions like adaptive voltage and frequency scaling.

show abstract

“…Hence, a flipwell device (NMOS on n-well) is used for this switch. Flipwell devices [15] are a standard feature for FDSOI technology. In a regular bulk-CMOS technology, this can be achieved by using a triple-well transistor.…”

Section: Mos Implementation Of the Sub-modulementioning

confidence: 99%

“…Additionally, a topology is proposed for the 5/2 mode which improves efficiency by reducing the bottom-plate parasitic loss as compared to a conventional series-parallel topology [12]. The converter was implemented in a 28nm FDSOI process [13]- [15] using only on-chip MOS and MOM (Metal-Oxide-Metal) capacitors that do not require any extra fabrication steps, unlike MIM (MetalInsulator-Metal) [6] and trench capacitors [5].…”

Section: Introductionmentioning

confidence: 99%

A 28 nm FDSOI Integrated Reconfigurable Switched-Capacitor Based Step-Up DC-DC Converter With 88% Peak Efficiency

Biswas

Sinangil

Chandrakasan

2015

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

Abstract-This paper presents a fully integrated, reconfigurable switched-capacitor based step-up DC-DC converter in a 28nm FDSOI process. Three reconfigurable step-up conversion ratios (5/2, 2/1, 3/2) have been implemented which can provide a wide range of output voltage from 1.2V to 2.4V with a nominal input voltage of 1V. We propose a topology for the 5/2 mode which improves the efficiency by reducing the bottomplate parasitic loss compared to a conventional series-parallel topology, while delivering the same amount of output power. Further, the proposed topology benefits from using core 1V devices for all charge-transfer switches without incurring any voltage overstress. The converter can deliver load current in the range of 10 µA to 500 µA, achieving a peak efficiency of 88%, using only on-chip MOS and MOM capacitors for a high density implementation.

show abstract

Multi-$V_{T}$ UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

Cited by 168 publications

References 15 publications

28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part I

28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part I

A Survey on Low-Power Techniques with Emerging Technologies

A 28 nm FDSOI Integrated Reconfigurable Switched-Capacitor Based Step-Up DC-DC Converter With 88% Peak Efficiency

Contact Info

Product

Resources

About