Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard

Gunnam, Kiran; Choi, Gwan; Wang, Weihuang; Yeary, Mark

doi:10.1109/iscas.2007.378835

Cited by 51 publications

(25 citation statements)

References 11 publications

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“…The process of decoding can be done with passing information through the edges of the graph. In this paper, we work with LDPC decoder based on our previous work presented in [18]- [19].…”

Section: Ldpc Decodermentioning

confidence: 99%

An Improved Soft Decision Based MIMO Detection Using Lattice Reduction

Rahman¹,

Rohani²,

Xu³

et al. 2014

IJCCE

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Abstract-This paper presents a performance analysis of soft decision based Lattice Reduction (LR) aided Schnorr-Euchner (SE) multiple-input-multiple-output (MIMO) detection algorithm with that of a hard one. We develop an advanced soft decoding scheme, for 4×4 MIMO with different modulation schemes and it provides 1.3 to 1.5 dB improvement compared to the LR-aided hard decision based detection method. The optimum parameters for K and saturation limit are further derived using extensive simulation. In the conventional K-best algorithm limiting the LLR values is not beneficiary in reducing the optimum size of candidate list, whereas applying the saturation limit on the LLR values in LR-aided algorithm will result in more than 8x reduction in list size as well as in the complexity of detector and LLR calculation unit.Index Terms-MIMO, soft decoding, lattice reduction, and k-best detector.

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“…The process of decoding can be done with passing information through the edges of the graph. In this paper, we work with LDPC decoder based on our previous work presented in [18]- [19].…”

Section: Ldpc Decodermentioning

confidence: 99%

An Improved Soft Decision Based MIMO Detection Using Lattice Reduction

Rahman¹,

Rohani²,

Xu³

et al. 2014

IJCCE

View full text Add to dashboard Cite

show abstract

“…In the past, several partially-parallel architectures have been proposed for the LDPC decoding [22,1,6,29,25,13,26,21]. However, they only deliver a throughput of a few hundreds of Mbps.…”

Section: Related Researchmentioning

confidence: 99%

“…However, processing of a single sub-matrix in isolation only requires a simple local communication network (switch) and a simple memory structure [22,1,6,29,25]. It does not solve the problem of an effective and efficient processing of the whole PCM matrix and related communication architecture for this aim.…”

Section: Case Study: Communication Architectures Of Ldpc Decodersmentioning

confidence: 99%

Scalable communication architectures for massively parallel hardware multi-processors

Jan

Jówiak

2012

Journal of Parallel and Distributed Computing

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“…QC-LDPC DECODER ARCHITECTURE LDPC codes and in particular quasi-cyclic (QC)-LDPC codes [7] are among the most popular and capable errorcorrecting codes adopted in many modern standards including DVB-S2 [8] and IEEE 802.11n [9]. The decoding of a QC-LDPC code is in general performed by iterative message passing between variable nodes which represent the code bits and check nodes which represent the parity check equations of the code-specific parity-check matrix H. The messages going from variable nodes to check nodes are denoted as Qmessages and the messages exchanged in the other direction as R-messages.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, an L-value is associated with each variable node representing the reliability information for the corresponding code bit in the form of an estimate of the aposteriori log-likelihood ratio (LLR). In this work, we use an LDPC decoder based on the offset-min-sum (OMS) messageupdate rules combined with the layered decoding schedule in order to profit from a good balance between convergence speed and VLSI implementation complexity [7], [4]. …”

Section: Introductionmentioning

confidence: 99%

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder

Meinerzhagen

Bonetti

Karakonstantis

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated with new data. These unique memory access statistics are taken advantage of by replacing all static standard-cell based memories (SCMs) of a prior-art LDPC decoder implementation by dynamic SCMs (D-SCMs), which are designed to retain data just long enough to guarantee reliable operation. The use of D-SCMs leads to a 44% reduction in silicon area of the LDPC decoder compared to the use of static SCMs. The low-power LDPC decoder architecture with refreshfree D-SCMs was implemented in a 90 nm CMOS process, and silicon measurements show full functionality and an information bit throughput of up to 600 Mbps (as required by the IEEE 802.11n standard).

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Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard

Cited by 51 publications

References 11 publications

An Improved Soft Decision Based MIMO Detection Using Lattice Reduction

An Improved Soft Decision Based MIMO Detection Using Lattice Reduction

Scalable communication architectures for massively parallel hardware multi-processors

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder

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