Multi-level reconfigurable architectures in the switch model

In this paper, we propose a multi-scale modeling approach for software architecture oriented to facilitate adaptability management. The proposed design approach is founded on UML notations and uses component diagrams. The diagrams are submitted to vertical and horizontal transformations for refinement; this is done to reach a fine-grain description that contains necessary details that characterize the architectural style. The intermediate models provide a description with a given abstraction that allow the validation to be conducted significantly while remaining tractable w.r.t. complexity. The validation scope can involve intrinsic properties ensuring the model correctness w.r.t. UML description. To achieve this, we propose a set of model refinement rules. The rules manage the refinement and abstraction process (vertical and horizontal) as a model transformation from a coarse-grain description to a fine-grain description. Finally, we experimented our approach by modeling an Emergency Response and Crisis Management System (ERCMS) as a case of study.

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“…Lange and Middendorf [6] introduced a multi-level concept for reconfigurable architectures with more than two levels.…”

Section: Related Workmentioning

confidence: 99%

Towards a multi-scale modeling approach for software architectures

Khlif

Kacem

et al. 2015

Proceedings of the 30th Annual ACM Symposium on Applied Computing

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“…In this section we give a brief introduction into (abstract) multi-level reconfigurable machines (as introduced in [8]). Only the so-called switch model is considered here which assumes that the machine has a set of n reconfigurable units (also called switches) which can be reconfigured independently of each other.…”

Section: Multi-level Reconfigurable Architecturesmentioning

confidence: 99%

“…The I-HD-Switch problem combines two subproblems: 1) finding the optimal points in the sequence of context requirements at which a reconfiguration operation should be performed at each level and 2) finding an optimal partition of the reconfiguration SRAM cells at each level. The first problem -for the case that the granularity is fine-grained so that there are n switches on each level -is called PHC-Switch problem and has been shown to be solvable in polynomial time in [8] by an algorithm called PHCSwitch algorithm. It is not hard to show that the first problem can also be optimally solved in polynomial time given a solution to the second subproblem using a weighted version of the PHC-Switch algorithm (each subset in the partitions of SRAM cells is treated as one switch which has as weight the size of the subset).…”

Section: Heuristics For the (I-)hd-switch Problemmentioning

confidence: 99%

“…Another concept is to adapt the actually available set of reconfigurable resources (and thus the number of reconfiguration bits that are necessary to define the state of the architecture during reconfiguration) to the actual needs during run time. Multi-level reconfigurable architectures possess such a property and can be dynamically reconfigured on different levels ( [7][8][9]). On the lowest reconfiguration level these architectures allow to perform ordinary reconfiguration operations, i.e., to define the state of routing units or the function of logic units.…”

Section: Introductionmentioning

confidence: 99%

“…Also the corresponding higher level contexts have to be defined such that the context requirements of the algorithm are satisfied. This problem has been called the Partition into Hypercontexts (ML-PHC-Switch) problem in [8]. There, it was shown that the ML-PHC-Switch problem can be solved by dynamic programming in time Oðnm 2 þ m 2 ðm þ nÞðr À 2Þ þ m 3 Þ.…”

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confidence: 99%

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Design Aspects of Multi-level Reconfigurable Architectures

Lange

Middendorf

2007

J Sign Process Syst Sign Image

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Dynamically reconfigurable hardware has already been deployed for accelerating computationally demanding applications. Some of these hardware architectures allow run time reconfiguration but this usually leads to a large reconfiguration overhead. The advantage of run time reconfiguration is that it allows new algorithmic solutions for many applications. To study the potential of frequent run time reconfiguration it is interesting to investigate its costs and benefits from an abstract point of view and to develop new architectural concepts. Multilevel reconfigurable architectures are one such concept that introduces several levels of reconfiguration. This paper deals with new types of multi-level reconfigurable architectures. The corresponding problem of finding the best granularity for different reconfiguration levels is formulated and investigated. Although this problem is shown to be NP-complete, an interesting restricted subcase is solved optimally in polynomial time. For the general case, a good heuristic is proposed that is based on solutions for the restricted case. Results on three example applications show that the reconfiguration cost can be reduced with the new architectures. Based on a proposed measure of relative efficiency it is also shown that the new architectures are more efficient so that they obtain a larger reconfiguration cost reduction with less additional hardware.

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