Multi-level programming of memristor in nanocrossbar

Zhu, Xuan; Wu, Chunqing; Tang, Yuhua; Wu, Junjie; Yi, Xun

doi:10.1587/elex.10.20130013

Cited by 4 publications

(4 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The blocks at the top and right of the nanocrossbar are programming circuits which are used to write and erase a nanocrossbar memory. The programming method has been proposed in our previous research [10], and will not be discussed later.…”

Section: Feedforward Layer Circuitmentioning

confidence: 99%

“…Here, by referring to the term memristor, we mean a variety of threshold type memristive devices which show a threshold voltage behavior [5]. Our design utilizes a nanocrossbar memory as the core component, based on the observation that nanocrossbar is a relatively mature fabrication process of integrating memristor devices, and many researches have been proposed considering its circuit design issue [9,10]. Through HSPICE simulation, pattern recognition and pattern classification function of Hamming network are demonstrated using a 16 × 16 nanocrossbar memory.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Hamming network circuits based on CMOS/memristor hybrid design

Zhu

Yang

et al. 2013

IEICE Electron. Express

Self Cite

View full text Add to dashboard Cite

Abstract:Memristor, as an innovative technology, has been proposed in the application of neural networks since its physical implementation was reported by HP lab. In this paper, we proposed a Hamming network circuits based on CMOS/memristor hybrid design which is compact in device size and circuit structure. Through HSPICE simulation, pattern recognition and classification functions of hamming network circuits are demonstrated using a 16 × 16 nanocrossbar memory.

show abstract

Section: Feedforward Layer Circuitmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Hamming network circuits based on CMOS/memristor hybrid design

Zhu

Yang

et al. 2013

IEICE Electron. Express

Self Cite

View full text Add to dashboard Cite

show abstract

“…Concerning the hardware implementation for specific target recognition applications on portable mobile platforms, we proposed a three-layer spiking convolutional neural networks (CNNs) with parallel architecture (SCNNs) [12]. Although, the convolutional neural networks are competent in tolerating the random effects, such as the device variations or circuit noise [13], they may significantly degrade the recognition accuracy rate [14,15]. Despite the multilevel memristor devices that have appeared [16,17,18,19], a better preparation technique has to be required since it still cannot be used for largescale applications.…”

Section: Introductionmentioning

confidence: 99%

Quaternary synapses network for memristor-based spiking convolutional neural networks

Sun

et al. 2019

IEICE Electron. Express

View full text Add to dashboard Cite

This paper proposes a method that renders the weights of the neural network with quaternary synapses map into the only four-level memristance of memristive devices. We show this method is capable of operating with a negligible loss in classification accuracy when the memristors utilized can store at least four unique values. Compared with other state-of-the-art methods, the method presented can achieve 98.65% accuracy under the 0.60M parameters. Systematic error analysis shows that the network can still reach over 95% accuracy under the condition of 95% yield of memristor crossbar array, 100 µV op-amp offset voltage and 0.5% Single-Pole-Double-Throw switches noise.

show abstract

“…However, device variations and manufacturing yield are still a big issue in memristor fabrication [19], [20], and the memristor may be damaged by testing cycles and aggressive programming. These situations will remarkably degrade the multiply-accumulate computation accuracy.…”

Section: Introductionmentioning

confidence: 99%

Cases Study of Inputs Split Based Calibration Method for RRAM Crossbar

Sun

et al. 2019

IEEE Access

View full text Add to dashboard Cite

Many mainstream applications require multiply-accumulate calculations, such as image processing and neuromorphic computing. Multiply-accumulate calculations using memristor crossbar arrays is a remarkable method for extremely high implementation efficiency, whereas the memristor array fabrication technology is still not mature and it is difficult to fabricate large-scale arrays with high-yield, which will seriously affect the performance of the application running on the RRAM crossbar. This paper proposes an inputs split based calibration method that improves the application accuracy in tolerating variations and stuck-at-fault of memristor devices. To demonstrate the performance of the calibration algorithm, the case of image sharpening and three neural networks architectures are applied for simulation experiments. And experimental results show that the calculation accuracy can be improved by up to 26.83% at 90% yield of crossbar arrays, and the success rate of the algorithm can be as high as 99.3% when there are several arrays cascaded. It is of great significance to the application of arrays in multiply-accumulate computation.

show abstract

Multi-level programming of memristor in nanocrossbar

Cited by 4 publications

References 7 publications

Hamming network circuits based on CMOS/memristor hybrid design

Hamming network circuits based on CMOS/memristor hybrid design

Quaternary synapses network for memristor-based spiking convolutional neural networks

Cases Study of Inputs Split Based Calibration Method for RRAM Crossbar

Contact Info

Product

Resources

About