Hamming network circuits based on CMOS/memristor hybrid design

Zhu, Xuan; Yang, Xuejun; Wu, Chunqing; Wu, Junjie; Yi, Xun

doi:10.1587/elex.10.20130404

Cited by 15 publications

(14 citation statements)

References 13 publications

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“…I o is the weighted summation of 8 I o,3 + 4 I o,2 + 2 I o,1 + I o,0 for recognizing ‘o’. The currents of I a , I i , I u , I e , and I o are compared with each other in the winner-take-all circuit [ 19 ] to decide which vowel is the best match with the voice input as shown in Figure 3 . Output a , Output i , Output u , Output e , and Output o are the output signals of the winner-take-all circuit.…”

Section: Methodsmentioning

confidence: 99%

Neuromorphic crossbar circuit with nanoscale filamentary-switching binary memristors for speech recognition

2014

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In this paper, a neuromorphic crossbar circuit with binary memristors is proposed for speech recognition. The binary memristors which are based on filamentary-switching mechanism can be found more popularly and are easy to be fabricated than analog memristors that are rare in materials and need a more complicated fabrication process. Thus, we develop a neuromorphic crossbar circuit using filamentary-switching binary memristors not using interface-switching analog memristors. The proposed binary memristor crossbar can recognize five vowels with 4-bit 64 input channels. The proposed crossbar is tested by 2,500 speech samples and verified to be able to recognize 89.2% of the tested samples. From the statistical simulation, the recognition rate of the binary memristor crossbar is estimated to be degraded very little from 89.2% to 80%, though the percentage variation in memristance is increased very much from 0% to 15%. In contrast, the analog memristor crossbar loses its recognition rate significantly from 96% to 9% for the same percentage variation in memristance.

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Section: Methodsmentioning

confidence: 99%

Neuromorphic crossbar circuit with nanoscale filamentary-switching binary memristors for speech recognition

2014

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“…Figure 2 a shows the complementary crossbar architecture which is composed of two memristor arrays of M + and M − [ 11 , 12 ]. The M − array in Fig.…”

Section: Methodsmentioning

confidence: 99%

“…2 The crossbar array architectures of binary memristors for pattern recognition. a The complementary crossbar architecture [ 11 , 12 ]. b The twin crossbar architecture [ 10 ] …”

Section: Methodsmentioning

confidence: 99%

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Comparative Study on Statistical-Variation Tolerance Between Complementary Crossbar and Twin Crossbar of Binary Nano-scale Memristors for Pattern Recognition

et al. 2015

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This paper performs a comparative study on the statistical-variation tolerance between two crossbar architectures which are the complementary and twin architectures. In this comparative study, 10 greyscale images and 26 black-and-white alphabet characters are tested using the circuit simulator to compare the recognition rate with varying statistical variation and correlation parameters.As with the simulation results of 10 greyscale image recognitions, the twin crossbar shows better recognition rate by 4 % on average than the complementary one, when the inter-array correlation = 1 and intra-array correlation = 0. When the inter-array correlation = 1 and intra-array correlation = 1, the twin architecture can recognize better by 5.6 % on average than the complementary one.Similarly, when the inter-array correlation = 1 and intra-array correlation = 0, the twin architecture can recognize 26 alphabet characters better by 4.5 % on average than the complementary one. When the inter-array correlation = 1 and intra-array correlation = 1, the twin architecture is better by 6 % on average than the complementary one. By summary, we can conclude that the twin crossbar is more robust than the complementary one under the same amounts of statistical variation and correlation.

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“…Using CMOS/memristor hybrid architecture and a two-part spike, Afifi et al demonstrated Spike-Timing-Dependent-Plasticity (STDP) learning implementation [5]. Zhu et al proposed an approach for implementing Hamming network based on hybrid CMOS/memristor circuit design [6], in which pattern recognition and classification were demonstrated.…”

Section: Introductionmentioning

confidence: 99%

An adaptive neural network A/D converter based on CMOS/memristor hybrid design

Wang

You

Liu

et al. 2014

IEICE Electron. Express

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A memristor is regarded as a promising device for modeling synapses in the realization of artificial neural systems for its nanoscale size, analog storage properties, low energy and non-volatility. In this letter, an adaptive T-Model neural network based on CMOS/memristor hybrid design is proposed to perform the analog-to-digital conversion without oscillations. The circuit is composed of CMOS neurons and memristor synapses. The A/D converter (ADC) is trained by the least mean square (LMS) algorithm. The conductance of the memristors can be adjusted to convert input voltages with different ranges, which makes the ADC flexible. Using memristors as synapses in neuromorphic circuits can potentially offer high density.

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Hamming network circuits based on CMOS/memristor hybrid design

Cited by 15 publications

References 13 publications

Neuromorphic crossbar circuit with nanoscale filamentary-switching binary memristors for speech recognition

Neuromorphic crossbar circuit with nanoscale filamentary-switching binary memristors for speech recognition

Comparative Study on Statistical-Variation Tolerance Between Complementary Crossbar and Twin Crossbar of Binary Nano-scale Memristors for Pattern Recognition

An adaptive neural network A/D converter based on CMOS/memristor hybrid design

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