Multi-cycle Test with Partial Observation on Scan-Based BIST Structure

Suzuki, Yasuo; Yamaguchi, Hisato; Makoto, Matsuzono; Kajihara, Seiji

doi:10.1109/ats.2011.34

Cited by 23 publications

(6 citation statements)

References 15 publications

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“…Multi-cycle test is thus one of the promising ways to achieve a good trade-off among the fault coverage, TAT and power consumption for POST. However, we raise two major issues that obstruct the effect of multi-cycle test to reduce the scan-in patterns for shorting the TAT of POST, which are Fault effects vanishing problem [13]- [16] and Fault Detection Degradation of capture patterns.…”

Section: ) the Low Power Consumptionmentioning

confidence: 99%

FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST

Al-Awadhi

Aono

Wang

et al. 2020

IEICE Trans. Inf. & Syst.

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Multi-cycle Test looks promising a way to reduce the test application time of POST (Power-on Self-Test) for achieving a targeted high fault coverage specified by ISO26262 for testing automotive devices. In this paper, we first analyze the mechanism of Stuck-at Fault Detection Degradation problem in multi-cycle test. Based on the result of our analysis we propose a novel solution named FF-Control Point Insertion technique (FF-CPI) to achieve the reduction of scan-in patterns by multi-cycle test. The FF-CPI technique modifies the captured values of scan Flip-Flops (FFs) during capture operation by directly reversing the value of partial FFs or loading random vectors. The FF-CPI technique enhances the number of detectable stuck-at faults under the capture patterns. The experimental results of ISCAS89 and ITC99 benchmarks validated the effectiveness of FF-CPI technique in scan-in pattern reduction for POST.

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Section: ) the Low Power Consumptionmentioning

confidence: 99%

FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST

Al-Awadhi

Aono

Wang

et al. 2020

IEICE Trans. Inf. & Syst.

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“…Since filling new values to the control FFs before observing the original captured values would affect the fault coverage. For compensating fault coverage loss, we employ multi-cycle scan test with partial observation [14], where the responses of CUT captured into the control FFs are compressed directly into an additional compactor (compactor B) during many captures (except the last capture) and the output (signatures) of compactor B are observed in shift mode as well as compactor A. Multi-cycle test consists of many capture cycles, which brings more chances of fault sensitization [15], and capturing the values of control FFs into compactor B during multiple clock cycles increases the number of fault detection chances. Therefore, even if the captured values of the control FFs are modified after the last capture, the loss of fault coverage could be compensated.…”

Section: Power Metricsmentioning

confidence: 99%

“…These faults should have less chance of detection due to the faulty value masking during multi-capture [14]. Observing the FF during multiple captures brings more chances for these faults detection.…”

Section: Factors For Fault Coverage Improvementmentioning

confidence: 99%

“…We consider that FFs in the SoC model are set-reset type flip-flops for area overhead computing. Since partial observation of FFs requires an additional compactor (consists of an XOR tree and a MISR) which causes 1.93% area overhead as 20% FFs observation [14], it will be included in our evaluation. In order to estimate the area overhead for the hybrid value filling, we evaluate the ratio of FFs that are controlled as the 0-filling and the adjacent value filling in the hybrid value filling for all circuits.…”

Section: Area Overhead (Investment) Estimationmentioning

confidence: 99%

“…The method selects some FFs of scan chain at logic design phase, and the values of the selected FFs are overwritten before starting scan-shift operation so as to reduce the switching activity associated with scan-out. Since filling new values to the selected FFs before observing the capture values at the FFs would result in fault coverage loss, we employ multi-cycle scan test with partial observation [14]. Capturing the FF values with multi-cycle before scan-shift operation brings more chances of fault sensitization, and observing the captured values of a part of scan FFs in many capture cycles brings more chances of fault detection.…”

Section: Introductionmentioning

confidence: 99%

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Scan-Out Power Reduction for Logic BIST

Wang

Suzuki

Kajihara

et al. 2013

IEICE Trans. Inf. & Syst.

Self Cite

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SUMMARYIn this paper we propose a novel method to reduce power consumption during scan testing caused by test responses at scan-out operation for logic BIST. The proposed method overwrites some flip-flops (FFs) values before starting scan-shift so as to reduce the switching activity at scan-out operation. In order to relax the fault coverage loss caused by filling new FF values before observing the capture values at the FFs, the method employs multi-cycle scan test with partial observation. For deriving larger scan-out power reduction with less fault coverage loss and preventing hardware overhead increase, the FFs to be filled are selected in a predetermined ratio. For overwriting values, we prepare three value filling methods so as to achieve larger scan-out power reduction. Experiment for ITC99 benchmark circuits shows the effectiveness of the methods. Nearly 51% reduction of scan-out power and 57% reduction of peak scanout power are achieved with little fault coverage loss for 20% FFs selection, while hardware overhead is little that only 0.05%.

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Storage and Counter Based Logic Built-In Self-Test

Pomeranz

2023

IEEE Access

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Recent reports of silent data corruption because of hardware faults in large data centers bring to the forefront the importance of in-field testing. In-field testing, enabled by logic built-in self-test (LBIST ), addresses defects that occur during the lifetime of a chip and ones that escaped manufacturing tests. A class of LBIST approaches for scan circuits store partitioned deterministic test data on-chip and produce tests by combining stored test data entries in one of two ways: (1) pseudo-random combinations are selected by linear-feedback shift-registers (LFSRs), or (2) deterministic combinations are stored on-chip as sets of indices of stored test data entries. This article introduces a third option where counters are used for forming combinations of stored test data entries. Counters do not require additional storage, and ensure complete fault coverage with a limited number of tests. Experimental results for benchmark circuits demonstrate the advantages of counters in the context where test data entries for on-chip storage are obtained by partitioning compressed deterministic tests, and the universally available on-chip decompression logic is used as part of the test application process.INDEX TERMS Full scan design, linear-feedback shift-register (LFSR), logic built-in self-test (LBIST ), on-chip test generation, test data compression.

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Multi-cycle Test with Partial Observation on Scan-Based BIST Structure

Cited by 23 publications

References 15 publications

FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST

FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST

Scan-Out Power Reduction for Logic BIST

Storage and Counter Based Logic Built-In Self-Test

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