Proceedings of the 2000 International Symposium on Physical Design 2000
DOI: 10.1145/332357.332391
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Multi-center congestion estimation and minimization during placement

Abstract: As technology advances, more and more issues need to be considered in the placement stage, e.g., wirelength, congestion, timing, coupling. It is very hard to consider all of them together at the same time. Thus it is good if we can optimize one cost function without affecting others. In this paper, we will study methods to optimize congestion in placement without inflicting degradations/violations in other objectives or constraint. We give a mathematical equation to predict the overflow within a region using a… Show more

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Cited by 33 publications
(30 citation statements)
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“…GENERAL APPROACH SPECIFIC TECHNIQUES using Rent's Rule [41] net bounding box w/ weighting [6] STATIC building Steiner trees [27] pin density [4] counting nets in each region [35] (uniform) wire density [30] PROBABILISTIC pseudo-constructive wirelength [18] probabilistic pattern routing [36] CONSTRUCTIVE generating routes using A*-search on a collapsed (2-d) routing grid [37] using FastRoute [39] within an integrated framework [11] …”
Section: Prior Workmentioning
confidence: 99%
“…GENERAL APPROACH SPECIFIC TECHNIQUES using Rent's Rule [41] net bounding box w/ weighting [6] STATIC building Steiner trees [27] pin density [4] counting nets in each region [35] (uniform) wire density [30] PROBABILISTIC pseudo-constructive wirelength [18] probabilistic pattern routing [36] CONSTRUCTIVE generating routes using A*-search on a collapsed (2-d) routing grid [37] using FastRoute [39] within an integrated framework [11] …”
Section: Prior Workmentioning
confidence: 99%
“…To improve a design's routability, one set of techniques focus on routability-driven placement procedures that rely on mechanisms for predicting routing congestion. There are many successful efforts in this area, including [7,8,9,10,11,14,16].…”
Section: Introductionmentioning
confidence: 99%
“…In modern designs, several new factors contribute to routing congestion including significantly-different wire size and spacing among the metal layers, sizes of inter-layer vias, various forms of routing blockages (e.g., reserved for power-grid, clock network, or IP blocks in an SoC), local congestion due to pin density and wiring inside a global-cell, and virtual pins located at the higher metal layers. However, none of the past estimation techniques such as [2], [11], [14], [15] capture these new sources of congestion comprehensively.…”
Section: Introductionmentioning
confidence: 99%