2017
DOI: 10.1016/j.mejo.2017.07.009
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MTCML: Analysis, design and optimization of an alternative shallow-depth multiple-tail current mode logic

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Cited by 7 publications
(29 citation statements)
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“…The three‐input XOR/XNOR logic is designed with low stacked pairs or shallow‐depth logical pairs 11 . It is suitable for low‐voltage applications.…”
Section: Low‐voltage Design Techniquesmentioning
confidence: 99%
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“…The three‐input XOR/XNOR logic is designed with low stacked pairs or shallow‐depth logical pairs 11 . It is suitable for low‐voltage applications.…”
Section: Low‐voltage Design Techniquesmentioning
confidence: 99%
“…It is suitable for low‐voltage applications. In shallow‐depth CML, the tail current is dissolved into multiple tails with total current equal to the primary current but with less depth from V DD to GND 11 . The reduced stages of the NMOS differential pair change to the PMOS differential pair connected to the supply voltage.…”
Section: Low‐voltage Design Techniquesmentioning
confidence: 99%
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