MTCML: Analysis, design and optimization of an alternative shallow-depth multiple-tail current mode logic

Low‐voltage and high‐speed stand‐alone multiple‐input complex gates for error correction coding applications

“…The three‐input XOR/XNOR logic is designed with low stacked pairs or shallow‐depth logical pairs 11 . It is suitable for low‐voltage applications.…”

“…It is suitable for low‐voltage applications. In shallow‐depth CML, the tail current is dissolved into multiple tails with total current equal to the primary current but with less depth from V DD to GND 11 . The reduced stages of the NMOS differential pair change to the PMOS differential pair connected to the supply voltage.…”

“…The minimum voltage of the proposed logic will be less than conventional source‐coupled logic with reduced supply voltage. Therefore, the three(four)‐input XOR gate in proposed logic or MTCML 11 is decomposed into a subnetwork of two or three‐input XOR gates in SCL structure at minimum voltage, as shown in Figure 3. The equivalent circuit for three‐input AND gate in proposed logic or MTCML 11 composes of a chain of two‐input AND gates in SCL structure in minimum voltage.…”

“…Therefore, the three(four)‐input XOR gate in proposed logic or MTCML 11 is decomposed into a subnetwork of two or three‐input XOR gates in SCL structure at minimum voltage, as shown in Figure 3. The equivalent circuit for three‐input AND gate in proposed logic or MTCML 11 composes of a chain of two‐input AND gates in SCL structure in minimum voltage. We will see that built four‐input XOR gate using a tree or a chain of two‐input XOR gates in SCL structure has a higher cost and delay than the proposed logic.…”

“…(A, F) Decomposing a three‐input AND gate in proposed logic or multiple‐tailed current mode logic (MTCML) 11 into a subnetwork of two‐input AND gates in source‐coupled logic (SCL) logic. (B, G) Decomposing a three‐input XOR gate in proposed logic or MTCML 11 into a subnetwork of two‐input XOR gates in SCL logic, (C, D, E, H) Decomposing a four‐input XOR gate in proposed logic or MTCML 11 into a subnetwork of two‐ or three‐input XOR gates in SCL logic…”