MsBV: A Memory Compression Scheme for Bit-Vector-Based Classification Lookup Tables

Abstract

Packet classification is widely used in Software-Defined Networking (SDN). At present, packet classification is mainly implemented by software, such as OpenvSwitch, which has the disadvantage of low performance. On the Field Programmable Gate Array (FPGA) platform, FPGA has the advantages of reconfigurability and high processing performance. The current work proposes the FPGA-based Bit-Vector algorithms in packet classification, which has the advantages of determining latency and high throughput. In the Bit-Vector-based algorithms, stringent memory resources in FPGA are wasted to store relatively useless wildcards because there are plenty of wildcards in the rules. A bit-vector-based memory compression scheme named Memory-shared Bit-Vector (MsBV) is proposed. MsBV adopts a memory-shared homogeneous two-dimensional pipeline architecture, and it can reduce memory consumption and ensure the correctness of packet classification. In MsBV, we reduce memory consumption better by rearranging the bit matrix. The experimental results show that MsBV saves about 43.69% memory resources, 57.53% the number of ALUTs, and 37.59% the number of Registers compared to StrideBV of 100K OpenFlow rules. INDEX TERMS Bit-vector, packet classification, memory compression, shared memory, field programmable gate array.

PipeCache: High Hit Rate Rule-Caching Scheme Based on Multi-Stage Cache Tables

“…Specifically, an OpenFlow rule can decide where the packet will be transferred or drop the packet according to the packet L1, L2, L3, and L4 headers, including physical switch ports, MAC addresses, IP addresses, TCP/UDP ports, and other headers. Before transferring the packet, OpenFlow Switch can change its packet header information [3][4][5].…”