PipeCache: High Hit Rate Rule-Caching Scheme Based on Multi-Stage Cache Tables

Yang, Jialun; Li, Tao; Yan, Ji; Li, Junnan; Li, Chenglong; Wang, Baosheng

doi:10.3390/electronics9060999

Cited by 8 publications

(2 citation statements)

References 23 publications

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“…Many research studies aim to use less TCAM space to forward the vast majority of traffic; this includes dependencies among rules, e.g., [22,23]. Devoflow [2] proposes sampling and trigger techniques to figure out elephant flows, deploying flow entries only for these elephant flows.…”

Section: Flow Table Cachingmentioning

confidence: 99%

Reducing Flow Table Update Costs in Software-Defined Networking

Wang,

Yang,

Yang

et al. 2023

Sensors

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In software-defined networking (SDN), the traffic forwarding delay highly depends on the latency associated with updating the forwarding rules in flow tables. With the increase in fine-grained flow control requirements, due to the flexible control capabilities of SDN, more rules are being inserted and removed from flow tables. Moreover, the matching fields of these rules might overlap since multiple control domains might generate different rules for similar flows. This overlap implies dependency relationships among the rules, imposing various restrictions on forwarding entries during updates, e.g., by following update orders or storing entries at specified locations, especially in flow tables implemented using ternary content addressable memory (TCAM); otherwise, mismatching or packet dropping will occur. It usually takes a while to resolve and maintain dependencies during updates, which hinders high forwarding efficiency. To reduce the delay associated with updating dependent rules, in this paper, we propose an updating algorithm for TCAM-based flow tables. We formulate the TCAM maintenance process as an NP-hard problem and analyze the inefficiency of existing moving approaches. To solve the problem, we propose an optimal moving chain for single rule updates and provide theoretical proof for its minimum moving steps. For multiple rules arriving at a switch simultaneously, we designed a dynamic approach to update concurrent entries; it is able to update multiple rules heuristically within a restricted TCAM region. As the update efficiency concerns dependencies among rules, we evaluate our flow table by updating algorithms with different dependency complexities. The results show that our approach achieves about 6% fewer moving steps than existing approaches. The advantage is more pronounced when the flow table is heavily utilized and rules have longer dependency chains.

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Section: Flow Table Cachingmentioning

confidence: 99%

Reducing Flow Table Update Costs in Software-Defined Networking

Wang,

Yang,

Yang

et al. 2023

Sensors

View full text Add to dashboard Cite

show abstract

“…Moreover, offloading the processing of packets that match the cached rules to the hardware accelerator can allow for making full use of parallel hardware and improve performance. Rule-caching schemes can vary according to different deployment scenarios [43]. The choice of caching policy is beyond the scope of this article; thus, we simply implement cached-rule tables with two different kinds of caching policies on the accelerator as use cases.…”

Section: Use Casesmentioning

confidence: 99%

AccelSDP: A Reconfigurable Accelerator for Software Data Plane Based on FPGA SmartNIC

et al. 2021

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Software-defined networking (SDN) has attracted much attention since it was proposed. The architecture of the SDN data plane is also evolving. To support the flexibility of the data plane, the software implementation approach is adopted. The software data plane of SDN is commonly implemented on a commercial off-the-shelf (COTS) server, executing an entire processing logic on a commodity CPU. With sharp increases in network capacity, CPU-based packet processing is overwhelmed. However, completely implementing the data plane on hardware weakens the flexibility. Therefore, hybrid implementation where a hardware device is adopted as the accelerator is proposed to balance the performance and flexibility. We propose an FPGA SmartNIC-based reconfigurable accelerator to offload some of the operation-intensive packet processing functions from the software data plane to reconfigurable hardware, thus improving the overall data plane performance while retaining flexibility. The accelerated software data plane has a powerful line-rate packet processing capability and flexible programmability at 100 Gbps and higher throughput. We offloaded a cached-rule table to the proposed accelerator and tested its performance with 100 GbE traffic. Compared with the software implementation, the evaluation result shows that the throughput can achieve a 600% improvement when processing small packets and a 100% increase in large packet processing, and the latency can be reduced by about 20× and 100×, respectively, when processing small packets and large packets.

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MixedCache: Enabling Flow Directed Rule-Caching Scheme based on Heterogeneous Cache for OpenFlow

Yang

Liu

et al. 2020

J. Phys.: Conf. Ser.

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OpenFlow switches in SDN use Multiple Flow Tables (MFTs) for fine-grained flow control. Commodity switches integrate hardware storage resources such as SRAM and TCAM to store flow tables to achieve high-speed lookups. Many increased flow tables are rapidly exhausting these hardware storage resources, which makes the switches have to balance high-speed search and massive storage. The rule-caching scheme is a popular method to solve this problem, which caches the most commonly used rules into hardware storage resources. The existing rule-caching schemes are based on single hardware storage resources, and they cannot flexibly adjust the caching strategy according to the traffic characteristics. Simultaneously, the deployed commodity switches face the problem of difficulty in changing the size of SRAM and TCAM. This paper innovatively proposes the MixedCache scheme, which makes full use of the hardware storage resources in the switch according to the skewed characteristics of network traffic. MixedCache stores the large flows in SRAM by exact match and stores the small flows in the TCAM by wildcard match. MixedCache does not need to change the size of the deployed switch hardware storage resources, but makes full use of existing resources. Compared with the rule-caching scheme based on the exact match, the cache hit rate can increase by up to 15.61%. Compared with the rule-caching scheme based on the wildcard match, the cache hit rate can increase by up to 29.69%.

show abstract

PipeCache: High Hit Rate Rule-Caching Scheme Based on Multi-Stage Cache Tables

Cited by 8 publications

References 23 publications

Reducing Flow Table Update Costs in Software-Defined Networking

Reducing Flow Table Update Costs in Software-Defined Networking

AccelSDP: A Reconfigurable Accelerator for Software Data Plane Based on FPGA SmartNIC

MixedCache: Enabling Flow Directed Rule-Caching Scheme based on Heterogeneous Cache for OpenFlow

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