MRAM Acceleration Core for Vector Matrix Multiplication and XNOR-Binarized Neural Network Inference

Gao, Shifan; Chen, Bing; Qu, Yiming; Zhao, Yi

doi:10.1109/vlsi-tsa48913.2020.9203740

Cited by 10 publications

(8 citation statements)

References 1 publication

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“…Binary/Ternary Neural Networks (BNN/TNN) [5]- [8] has created an opportunity to realize computational benefits by exploiting inherent analog computing capabilities of emerging resistive memories [9], [10]. Some of the NVM (non-volatile memory) technologies explored for IMC applications for analog multiplication include: Flash [11], [12], RRAM (resistive random access memory) [3], [13]- [16], and MRAM (magnetoresistive RAM) [17], [18]. RRAM based XNOR bitcells provide following advantages: (i) less area and non-volatility compared to SRAM (≈150 F 2 per bitcell), (ii) lower operating voltages and faster memory access time compared to Flash, and (iii) lower fabrication cost, reduced area and write energy compared to MRAM.…”

Section: Introductionmentioning

confidence: 99%

Time-Multiplexed In-Memory Computation Scheme for Mapping Quantized Neural Networks on Hybrid CMOS-OxRAM Building Blocks

Kingra

Parmar

Sharma

2022

IEEE Trans. Nanotechnology

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In this work, we experimentally demonstrate two key building blocks for realizing Binary/Ternary Neural Networks (BNNs/TNNs): (i) 130 nm CMOS based sigmoidal neurons and (ii) HfOx based multi-level (MLC) OxRAM-synaptic blocks. An optimized vector matrix multiplication programming scheme that utilizes the two building blocks is also presented. Compared to prior approaches that utilize differential synaptic structures, a single device per synapse with two sets of READ operations is used. Proposed hardware mapping strategy shows performance change of <5% (decrease of 2-5% for TNN, increase of 0.2% for BNN) compared to ideal quantized neural networks (QNN) with significant memory savings in the order of 16-32× for classification problem on Fashion MNIST (FMNIST) dataset. Impact of OxRAM device variability on the performance of Hardware QNN (BNN/TNN) is also analyzed.

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Section: Introductionmentioning

confidence: 99%

Time-Multiplexed In-Memory Computation Scheme for Mapping Quantized Neural Networks on Hybrid CMOS-OxRAM Building Blocks

Kingra

Parmar

Sharma

2022

IEEE Trans. Nanotechnology

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“…To overcome the above challenges posed by DNNs and interchip communications, on-chip in-memory BNNs with XNOR accumulation have been explored [2], [3], [5], [6], [10], [13], [17]. In [2], [13] in-memory BNN based on 6T and 8T SRAMs are demonstrated.…”

Section: Introductionmentioning

confidence: 99%

STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural Networks

Pham

Trinh

Chang

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this paper, a row-wise XNOR accumulator architecture for STT-MRAM arrays is proposed for parallel and efficient multiply-and-accumulate (MAC) operation. The proposed accumulator supports in-memory computing and binary neural network (BNN) applications. In the proposed architecture, inputs are fed from the complementary bitlines, whereas readout is performed through a time-based sense amplifier (TBS). The proposed architecture that does not require any ADC can exhibit an average error rate of 0.085 for XNOR vector size (i.e., accumulate capacity) of 128 bits, which translates into 98.45% classification accuracy of a multi-layer perceptron (MLP) on the MNIST dataset.

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“…In CIM design, the processing speed of memory for AI calculation is an important factor that cannot be ignored, as well as low power. To meet these requirements, various next-generation memories such as Resistive RAM (RRAM) [7][8][9][10] and Magnetoresistive RAM (MRAM) [11,12] are emerging; however, as shown in Table 1, their speed is still lagging behind SRAM [13,14]. For this reason, SRAM has been considered the most suitable memory for CIM designs in recent years.…”

Section: Introductionmentioning

confidence: 99%

A Novel Ultra-Low Power 8T SRAM-Based Compute-in-Memory Design for Binary Neural Networks

Kim

Yadav

et al. 2021

Electronics

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We propose a novel ultra-low-power, voltage-based compute-in-memory (CIM) design with a new single-ended 8T SRAM bit cell structure. Since the proposed SRAM bit cell uses a single bitline for CIM calculation with decoupled read and write operations, it supports a much higher energy efficiency. In addition, to separate read and write operations, the stack structure of the read unit minimizes leakage power consumption. Moreover, the proposed bit cell structure provides better read and write stability due to the isolated read path, write path and greater pull-up ratio. Compared to the state-of-the-art SRAM-CIM, our proposed SRAM-CIM does not require extra transistors for CIM vector-matrix multiplication. We implemented a 16 k (128 × 128) bit cell array for the computation of 128× neurons, and used 64× binary inputs (0 or 1) and 64 × 128 binary weights (−1 or +1) values for the binary neural networks (BNNs). Each row of the bit cell array corresponding to a single neuron consists of a total of 128 cells, 64× cells for dot-product and 64× replicas cells for ADC reference. Additionally, 64× replica cells consist of 32× cells for ADC reference and 32× cells for offset calibration. We used a row-by-row ADC for the quantized outputs of each neuron, which supports 1–7 bits of output for each neuron. The ADC uses the sweeping method using 32× duplicate bit cells, and the sweep cycle is set to 2N−1+1, where N is the number of output bits. The simulation is performed at room temperature (27 °C) using 45 nm technology via Synopsys Hspice, and all transistors in bitcells use the minimum size considering the area, power, and speed. The proposed SRAM-CIM has reduced power consumption for vector-matrix multiplication by 99.96% compared to the existing state-of-the-art SRAM-CIM. Furthermore, because of the decoupled reading unit from an internal node of latch, there is no feedback from the reading unit, with read static noise, and margin-free results.

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MRAM Acceleration Core for Vector Matrix Multiplication and XNOR-Binarized Neural Network Inference

Cited by 10 publications

References 1 publication

Time-Multiplexed In-Memory Computation Scheme for Mapping Quantized Neural Networks on Hybrid CMOS-OxRAM Building Blocks

Time-Multiplexed In-Memory Computation Scheme for Mapping Quantized Neural Networks on Hybrid CMOS-OxRAM Building Blocks

STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural Networks

A Novel Ultra-Low Power 8T SRAM-Based Compute-in-Memory Design for Binary Neural Networks

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