MOSFET series resistance extraction at cryogenic temperatures

Abstract

A series resistance extraction method recently proposed, which uses multiple drain current vs. gate voltage curves at varied drain voltages, was applied to bulk CMOS devices at low temperatures down to 4 K. Moderate reduction of series resistance compared with 300 K was found. Horizontal field dependence of mobility significantly changed with temperature, which was taken into account during the extraction. Anomalous non-linear series resistance was observed at 4 K only for p-channel FETs, suggesting need for careful source/drain overlap design for low temperature operations.

Investigation of long channel bulk MOSFETs threshold voltage model down to 10 mK and key analog parameters at 4 K

“…Characterization 1–6 and modeling 7–15 works of key device parameters, such as threshold voltage of metal‐ oxide‐semiconductor field‐effect transistor (MOSFET) in cryogenic temperature targeting for quantum computing 16–18 have gathered increasing research attention. However, most studies have been focusing around 4 K temperature because most interfacing CMOS chips are placed in this temperature regime 5,19–22 .…”