MOSFET gate dimension dependent drain and source leakage modeling by standard SPICE models

Paňko, Václav; Banas, Stanislav; Prejda, Dusan; Dobeš, Josef

doi:10.1016/j.sse.2013.01.001

Cited by 5 publications

(2 citation statements)

References 8 publications

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“…The modeling of submicron MOSFETs is researched in Djahli et al, 13 Imam et al, 14 and Zhang et al 15 In Park et al, 16,17 the modeling of the non-quasi-static analytical model of longchannel MOSFETs is focused on. In Panko et al, 18 the impact of several parasitic bipolar devices is considered based on standard MOSFET models (BSIM3/BSIM4). Sarvaghad-Moghaddam et al 19 and Tang and Li 20 conducted research on the modeling of nanoscale MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

A MOSFET EMC modeling method based on electrical characteristic measurement and simplex optimization and particle swarm optimization

Pan,

Liu,

Ren

et al. 2023

Circuit Theory & Apps

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SummaryMetal oxide semiconductor field effect transistors (MOSFETs) are widely used in various power electronic systems, and the establishment of the electromagnetic compatibility (EMC) model for MOSFETs is crucial for EMC analysis of these systems, especially high‐frequency switching circuits. In this paper, a MOSFET EMC modeling method is proposed based on electrical characteristic measurement, simplex optimization, and particle swarm optimization (PSO), to make MOSFET models meet both functionality and EMC analysis requirements. First, systematic methods for extracting SPICE parameters based on physical MOSFETs are presented, including a proposed curve‐fitting method based on PSO for extracting the CDS‐VDS and ID‐VGS characteristic parameters. Second, parametric influence analyses are conducted on some important model parameters, and the law that these parameters affect the EMC of MOSFETs is obtained. Finally, the preliminary MOSFET model was optimized comprehensively using the simplex method. The measured and simulated results are in good agreement in both time domain and frequency domain. It proves that the established model meets the requirements for model accuracy in terms of both EMC and functionality. Therefore, the proposed EMC modeling method is feasible.

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Section: Introductionmentioning

confidence: 99%

A MOSFET EMC modeling method based on electrical characteristic measurement and simplex optimization and particle swarm optimization

Pan,

Liu,

Ren

et al. 2023

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…To investigate such a typical behavior, we have done various technology computeraided design (TCAD) simulations 13) for various conditions of drain to source voltage (V DS ), gate to source voltage (V GS ), body to source voltage (V BS ), channel length (L eff ), and channel doping (N SUB ). There are lot of leakage current models in the literature; [14][15][16][17][18][19][20][21][22][23][24][25][26][27] but no one has modeled such bias dependency on punch-through mainly for the weak inversion region. In this work we propose a model for zero-V TH devices within the frame work of industry-standard BSIM6 model of bulk MOSFET.…”

Section: Introductionmentioning

confidence: 99%

Analysis and modeling of zero-threshold voltage native devices with industry standard BSIM6 model

Gupta

Agarwal

Lin

et al. 2017

Jpn. J. Appl. Phys.

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In this paper, we present the modeling of zero-threshold voltage (VTH) bulk MOSFET, also called native devices, using enhanced BSIM6 model. Devices under study show abnormally high leakage current in weak inversion, leading to degraded subthreshold slope. The reasons for such abnormal behavior are identified using technology computer-aided design (TCAD) simulations. Since the zero-VTH transistors have quite low doping, the depletion layer from drain may extend upto the source (at some non-zero value of VDS) which leads to punch-through phenomenon. This source–drain leakage current adds with the main channel current, causing the unexpected current characteristics in these devices. TCAD simulations show that, as we increase the channel length (Leff) and channel doping (NSUB), the source–drain leakage due to punch-through decreases. We propose a model to capture the source–drain leakage in these devices. The model incorporates gate, drain, body biases and channel length as well as channel doping dependency too. The proposed model is validated with the measured data of production level device over various conditions of biases and channel lengths.

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Modeling and analysis of sub-surface leakage current in nano-MOSFET under cutoff regime

Swami

Rai

2017

Superlattices and Microstructures

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MOSFET gate dimension dependent drain and source leakage modeling by standard SPICE models

Cited by 5 publications

References 8 publications

A MOSFET EMC modeling method based on electrical characteristic measurement and simplex optimization and particle swarm optimization

A MOSFET EMC modeling method based on electrical characteristic measurement and simplex optimization and particle swarm optimization

Analysis and modeling of zero-threshold voltage native devices with industry standard BSIM6 model

Modeling and analysis of sub-surface leakage current in nano-MOSFET under cutoff regime

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