MOSFET conductance modelling including distortion analysis aspects

Abstract

The nanotechnology trenzd needs more precisely nmodels for active devices. From? this point of view the design of linear analog circuits lacks mtodels for state-of-the-art MOS transistors to accuratelv describe the conductance and distortiont effects. This is mainly due to inaccu-crate modellintg of the second order effects induced by high vertical gate field such as nmobility degradation and short channel series resistance and second order effects induced by parallel drain field like velocity saturation in the ohmic region and channel length ,znodlulation in the saturation regioni. After a rigorouis description of transistor conzductance in ohmic and satuiration region we included these effects in the MOS tranisistor model, using a compact expression of drain currenit for computation reasons. The sinzmulations using the niew drain cuirrent expression were in good agreement with experimental data.