MOS-Only Memristor Emulator

Srivastava, Pushkar; Gupta, Rahul Kumar; Sharma, Rohit; Ranjan, Rajeev Kumar

doi:10.1007/s00034-020-01421-x

Cited by 27 publications

(12 citation statements)

References 27 publications

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“…3) The memristor model in [19] operates at a power supply of ± 0.9V hence the power consumption is relatively larger when compared with the proposed model. 4) A new circuit configuration emulating the memristive behavior comprising only PMOS along with a capacitor is utilized when compared with the work in [20]. 5) While the design in [20] also offers zero static power consumption, its operation and hence the hysteresis is entirely dependent on the parasitic capacitances of the device which puts a lot of constraint in determining the memory states of the memristor.…”

Section: Comparison With Existing Memristor Emulatormentioning

confidence: 99%

“…4) A new circuit configuration emulating the memristive behavior comprising only PMOS along with a capacitor is utilized when compared with the work in [20]. 5) While the design in [20] also offers zero static power consumption, its operation and hence the hysteresis is entirely dependent on the parasitic capacitances of the device which puts a lot of constraint in determining the memory states of the memristor. In other words, the control over the capacitance is lost whereas the design presented here has the added advantage of tunability since the capacitor is externally connected to the circuit and can be tuned as per the requirement.…”

Section: Comparison With Existing Memristor Emulatormentioning

confidence: 99%

“…The work in [19] constitutes a memristor emulator with four transistors operating up to 100MHz. Also, a new passive floating/grounder memristor emulator has been reported in [20] while Ghosh et al in [21] presented the work with three N-type MOS having a power consumption of 2.6 µW. Meanwhile, some other works of literature containing memristor emulator circuits are reported in [22]- [24].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

New Zero Power Memristor Emulator Model and Its Application in Memristive Neural Computation

et al. 2023

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We present here a simple three P-type MOSFET-based grounded memristor emulator model. The model is designed to achieve zero static power dissipation and is done so by eliminating the external DC supply i.e., no DC bias. The proposed memristor emulator model has extremely low dynamic power dissipation as well which comes to around 175 nW i.e., ∼ 67 % improvement compared to recent work. A mathematical analysis is carried out to present the relevance of this design. Simulations were done on Cadence Virtuoso 90 nm technology node and fingerprints of the proposed memristor emulator were obtained. The layout area occupied by the model is approx 1154.69 µm 2 and an external capacitor is connected to add tunability to the circuit. Furthermore, Monte Carlo and corner analysis validate the robust nature of the design. Besides, simulations have been experimentally verified using CD-4007 CMOS integrated circuit (IC) to make the design practically feasible. Furthermore, the design offers advantages such as extremely less overall power consumption and smaller chip area that could possibly pave the path for fabrication using standard CMOS technologies. At last, an application of the proposed model depicting in-memory computation through a memristor emulator crossbar array is presented in brief.

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Section: Comparison With Existing Memristor Emulatormentioning

confidence: 99%

Section: Comparison With Existing Memristor Emulatormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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New Zero Power Memristor Emulator Model and Its Application in Memristive Neural Computation

et al. 2023

Self Cite

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“…8 A proven approach to reducing the occupied chip area of a memristor emulator is to reduce or even eliminate the active and passive components in the memristor emulator. For example, MOS-only memristor emulators 8,16,[20][21][22][23][24] are only constructed with transistors 24 and have the simple topology, that is, have the small occupied chip area. On the other hand, MOS-only memristor emulators only use the intrinsic capacitance of the transistor to realize the memory characteristics of the memristor, which means that the operating frequency of MOS-only memristor emulator can increase as the size of the transistor decreases.…”

Section: Introductionmentioning

confidence: 99%

A GHz‐level memristor emulator with only MOSFET

Zhou,

Wang,

Chen

2023

Circuit Theory & Apps

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SummaryThe MOS‐only memristor only uses the transistor's intrinsic capacitance to realize the memristor's memory effect, which is beneficial to increase its operating frequency and reduce its occupied chip area. This paper proposes a GHz‐level MOS‐only memristor emulator (i.e., PGME and NGME). PGME/NGME consists of three/four MOSFETs without any external elements and power supplies. The operating frequency of PGME/NGME is high up to 5 GHz. When the three/four MOSFETs in PGME are pch_hvts of TSMC's 65‐nm process, the occupied chip areas of PGME‐3, PGME‐4A, and PGME‐4B are 3.9 ∗ 2.7 m2, 4.3 ∗ 3.3 m2, and 4.3 ∗ 4.4 m2, respectively. The minimum step time of material implication circuit based on PGME‐3 and NGME‐3 is only 70 ps. Additionally, a chaotic oscillator circuit based on PGME‐4A is presented and verified with discrete p‐channel MOSFETs of CD4007.

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“…In 2008, HP Labs proved the physical existence of memristor for the first time, responding to Professor Cai's speculation [2]. Since then, the related theoretical research of memristor has entered the practical stage, which has attracted strong attention from researchers [3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Dynamic Behaviors Analysis of a Novel Fractional-Order Chua’s Memristive Circuit

Zhang

Liu

et al. 2021

Mathematical Problems in Engineering

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This paper proposed a novel fractional-order Chua’s memristive circuit. Firstly, a fractional-order mathematical model of a diode bridge generalized memristor with RLC filter cascade is established, and simulations verify that the fractional-order generalized memristor satisfies the basic characteristics of a memristor. Secondly, the capacitor and inductor in Chua’s chaotic circuit are extended to the fractional order, and the fractional-order generalized memristor is used instead of Chua’s diode to establish the fractional-order mathematical model of chaotic circuit based on RLC generalized memristor. By studying the stability analysis of the equilibrium point and the influence of the circuit parameters on the system dynamics, the dynamic characteristics of the proposed chaotic circuit are theoretically analyzed and numerically simulated. The results show that the proposed fractional-order memristive chaotic circuit has gone through three states: period, bifurcation, and chaos, and a narrow period window appears in the chaotic region. Finally, the equivalent circuit method is adopted in PSpice to realize the construction of the fractional-order capacitance and inductance, and the simulation of the fractional-order memristive chaotic circuit is completed. The results further verify the correctness of the theoretical analysis.

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MOS-Only Memristor Emulator

Cited by 27 publications

References 27 publications

New Zero Power Memristor Emulator Model and Its Application in Memristive Neural Computation

New Zero Power Memristor Emulator Model and Its Application in Memristive Neural Computation

A GHz‐level memristor emulator with only MOSFET

Dynamic Behaviors Analysis of a Novel Fractional-Order Chua’s Memristive Circuit

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