MOS Integrated Circuit Reliability

Schnable, G. L.; Ewald, Henry J.; Schlegel, E. S.

doi:10.1109/tr.1972.5216165

Cited by 15 publications

(6 citation statements)

References 21 publications

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“…The inversion voltage under metal lines over field oxide of commercially available MOS-integrated circuits can be degraded to the point where the operating voltage causes channeling between two isolated p-regions and degrades or fails the circuit (25).…”

Section: Discussionmentioning

confidence: 99%

A Negative-Ion Type Instability in MOS Devices

Schlegel

Schnable

1972

J. Electrochem. Soc.

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A hot-bias instability capable of shifting threshold voltages to positive values has been observed in the field oxide of MOS devices that have stable gate oxides. The instability is attributed to a contaminant that is introduced during thermal oxidation or other high-temperature processes, and is believed to be due to an immobile negative ion coexistent with a mobile positive ion. The activation energy and mobility of the mobile charge are similar to that of sodium in SiO2. The effects of differences in processing are discussed.

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Section: Discussionmentioning

confidence: 99%

A Negative-Ion Type Instability in MOS Devices

Schlegel

Schnable

1972

J. Electrochem. Soc.

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“…With complex IC's, increased electrical and visual inspection yields frequently more than compensate for the costs of applying and delineating a passivation layer. Glass passivation layers, deposited over the metallization pattern, have also been shown to significantly increase device reliability (197,97,276,125,185,324,127).…”

Section: Passivation Layers and Silicon Device Reliabilitymentioning

confidence: 99%

“…Early silicon devices were primarily sealed in hermetic packages. The plastic-encapsulated silicon devices initially offered had reliability limitations (183,215,310,36,276,98,108,3.04) which, to a large extent, have now been overcome (24,95,98,165,113). Plastic encapsulation does permit lower costs, provides mechanically rugged packages, provides freedom from loose particle problems, and permits smaller package size.…”

Section: Device Encapsulationmentioning

confidence: 99%

Passivation Coatings on Silicon Devices

Schnable

Kern

Comizzoli

1975

J. Electrochem. Soc.

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Passivation coatings are widely used to improve the performance and reliability of silicon devices of various types, ranging from discrete mesa‐type diodes and transistors to complex planar silicon integrated circuits, and including both hermetic and plastic‐encapsulated devices. This paper reviews the materials and techniques used to apply passivation coatings to completed silicon devices. Principal production techniques used in passivation of silicon devices include thermal oxidation, high‐temperature diffusion, high‐temperature chemical vapor deposition of Si3N4 or Al2O3 , low‐temperature chemical vapor deposition of glasslike SiO2 or phosphosilicate layers (deposited at approximately 400°C), rf sputtering of SiO2 , mechanical deposition of glass frit layers which are subsequently fused, and application of organic polymer films.The effects of passivation layers on silicon device reliability are discussed, and the interrelationships among the silicon device, the passivation layer or layers used and the final encapsulation are indicated. Pertinent references on passivation and on related topics are cited in the text.

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“…Significant improvements in terms of gate oxide reliability were achieved [2][3][4][5][6]. Significant improvements in terms of gate oxide reliability were achieved [2][3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Optimization of Poly-silicon Process for 3C-SiC Based MOS Devices

et al. 2010

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The electrical properties of wet oxides with poly-silicon gates fabricated on n-type 3C-SiC (001) epilayers have been studied. Five alternatives have been considered for the activation of the poly-silicon layer. The influence of two main parameters has been thought-out: the process type (thermal annealing or rapid thermal annealing) and the gas species composing the annealing atmosphere (argon, dry or wet oxygen). The poly-Si activation process combining RTA and argon as ambient demonstrates minimal thermal budget and superior preservation of the oxide quality. The fabricated MOS structures demonstrate high electrical properties and reliability of the oxide. That results in a small negative flat band voltage shift of -0.9 V and in an interface state density D it of 7.4 × 10 10 eV -1 cm -2 at 0.63 eV below the conduction band. The TZDB measurements revealed an average breakdown electric field of 9.4 MV/cm.

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MOS Integrated Circuit Reliability

Cited by 15 publications

References 21 publications

A Negative-Ion Type Instability in MOS Devices

A Negative-Ion Type Instability in MOS Devices

Passivation Coatings on Silicon Devices

Optimization of Poly-silicon Process for 3C-SiC Based MOS Devices

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