More Flops or More Precision? Accuracy Parameterizable Linear Equation Solvers for Model Predictive Control

Roldao-Lopes, Antonio; Shahzad, Amir; Constantinides, George A.; Kerrigan, Eric C.

doi:10.1109/fccm.2009.19

Cited by 21 publications

(24 citation statements)

References 20 publications

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“…Current high-performance multicore and manycore systems (aka "CPUs" and "GPUs") do provide a few data types that can be used to adjust data precision (i.e., 8/16/32/64-bit integers and 16/32/64-bit floating-point representations). Moreover, within reconfigurable computing architectures based on field-programmable gate arrays (FPGAs), the wordlength can be adjusted according to the algorithm specification [17], [18]. However, the problem of allocating optimal wordlength per input data component, memory, and interconnect unit is known to be NP hard [17], [18] and one can only provide for a static configuration (and precision) during runtime [17].…”

Section: Error Tolerance In Multimedia Stream Processing Systemsmentioning

confidence: 99%

“…Moreover, within reconfigurable computing architectures based on field-programmable gate arrays (FPGAs), the wordlength can be adjusted according to the algorithm specification [17], [18]. However, the problem of allocating optimal wordlength per input data component, memory, and interconnect unit is known to be NP hard [17], [18] and one can only provide for a static configuration (and precision) during runtime [17]. Thus, while the computing architecture can be configured for a specific algorithm [18], a completely new configuration will be required for a different algorithm (or, in most cases, even for a different precision requirement).…”

Section: Error Tolerance In Multimedia Stream Processing Systemsmentioning

confidence: 99%

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Error Tolerant Multimedia Stream Processing: There's Plenty of Room at the Top (of the System Stack)

Andreopoulos

2013

IEEE Trans. Multimedia

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Abstract-There is a growing realization that the expected fault rates and energy dissipation stemming from increases in CMOS integration will lead to the abandonment of traditional system reliability in favor of approaches that offer reliability to hardware-induced errors across the application, runtime support, architecture, device and integrated-circuit (IC) layers. Commercial stakeholders of multimedia stream processing (MSP) applications, such as information retrieval, stream mining systems, and high-throughput image and video processing systems already feel the strain of inadequate system-level scaling and robustness under the always-increasing user demand. While such applications can tolerate certain imprecision in their results, today's MSP systems do not support a systematic way to exploit this aspect for cross-layer system resilience. However, research is currently emerging that attempts to utilize the error-tolerant nature of MSP applications for this purpose. This is achieved by modifications to all layers of the system stack, from algorithms and software to the architecture and device layer, and even the IC digital logic synthesis itself. Unlike conventional processing that aims for worst-case performance and accuracy guarantees, error-tolerant MSP attempts to provide guarantees for the expected performance and accuracy. In this paper we review recent advances in this field from an MSP and a system (layer-by-layer) perspective, and attempt to foresee some of the components of future cross-layer error-tolerant system design that may influence the multimedia and the general computing landscape within the next ten years.

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Section: Error Tolerance In Multimedia Stream Processing Systemsmentioning

confidence: 99%

Section: Error Tolerance In Multimedia Stream Processing Systemsmentioning

confidence: 99%

Error Tolerant Multimedia Stream Processing: There's Plenty of Room at the Top (of the System Stack)

Andreopoulos

2013

IEEE Trans. Multimedia

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“…Algorithms that target embedded platforms are available in FiOrdOs [8], FORCES [5], CVXGEN [9], qpOASES [3], and MPT3 [10], just to name a few. Earlier work on the implementation aspects of MPC on embedded hardware are reported in [11], [12], [13], [14], [15], [7], where a common goal is the efficient use of resource constrained embedded hardware. Steps towards real-time guarantees or effects of limited computation time on MPC stability and feasibility have also been made in recent research work [16], [17].…”

Section: Introductionmentioning

confidence: 99%

Embedded Model Predictive Control on a PLC using a primal-dual first-order method for a subsea separation process

Kufoalor

Richter

Imsland

et al. 2014

22nd Mediterranean Conference on Control and Automation

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Abstract-The results of a PLC implementation of embedded Model Predictive Control (MPC) for an industrial problem are presented in this paper. The embedded MPC developed is based on the linear MPC module in SEPTIC (Statoil Estimation and Prediction Tool for Identification and Control), and it combines custom ANSI C code generation with problem size reduction methods, embedded real-time considerations, and a primal-dual first-order method that provides a fast and light QP solver obtained from the FiOrdOs code generator toolbox. Since the primal-dual first-order method proposed in this paper is new in the control community, an extensive comparison study with other state-of-the-art first-order methods is conducted to underline its potential. The embedded MPC was implemented on the ABB AC500 PLC, and its performance was tested using hardware-in-the-loop simulation of Statoil's newly patented subsea compact separation process. A warm-start variant of the proposed first-order method outperforms a tailored interiorpoint method by a factor of 4 while occupying 40% less memory.

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“…Section 10 in [7]). Other researchers have also considered this approach within the MPC context [19].…”

mentioning

confidence: 99%

“…In some cases, it is acceptable to stop the method after just a few iterations. This reduces the overall complexity while often delivering good approximate solutions [19]. To be clear, we are interested in using a conjugate gradient method for solving Hρ = g, which only affects line 3 in Algorithm 1.…”

mentioning

confidence: 99%

Implementation of linear model predictive control using a field-programmable gate array

Mills

Wills

Weller

et al. 2012

IET Control Theory &Amp; Applications

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The paper investigates the design of a field programmable gate array based custom computer architecture solution for implementing model predictive control. The solution employs a primal logarithmic-barrier interior-point algorithm in order to handle actuator constraints. The solution also incorporates practical aspects of a control algorithm including state observation and data sampling. The resulting circuit is profiled by application to a disturbance rejection control problem of a 14'th order lightly damped flexible beam structure with actuator constraints. This is achieved at 2 kHz sampling frequency and with 16-sample prediction horizon.

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More Flops or More Precision? Accuracy Parameterizable Linear Equation Solvers for Model Predictive Control

Cited by 21 publications

References 20 publications

Error Tolerant Multimedia Stream Processing: There's Plenty of Room at the Top (of the System Stack)

Error Tolerant Multimedia Stream Processing: There's Plenty of Room at the Top (of the System Stack)

Embedded Model Predictive Control on a PLC using a primal-dual first-order method for a subsea separation process

Implementation of linear model predictive control using a field-programmable gate array

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