Abstract:The paper investigates the design of a field programmable gate array based custom computer architecture solution for implementing model predictive control. The solution employs a primal logarithmic-barrier interior-point algorithm in order to handle actuator constraints. The solution also incorporates practical aspects of a control algorithm including state observation and data sampling. The resulting circuit is profiled by application to a disturbance rejection control problem of a 14'th order lightly damped … Show more
“…Compared with [5], our TSA-based linear solver is ∼ 12× faster though no resource consumption results are available for comparison of area. From the power consumption perspective, actual processing utilization for our TSA-based SA design is low when compared to a 1D SA design.…”
Section: B Implementation Resultsmentioning
confidence: 99%
“…Our proposed design implements signed fixed-point number format with 9 integer bits and 8 binary bits, similar to [5], however our design differs in being wordlength and matrix size parameterizable at the PE level within the SA architecture. We make use of the DSP Blocks' dynamic configurability [6] to support multiple operations on the same hardware in different steps.…”
Section: A System Setupmentioning
confidence: 99%
“…The individual blocks are designed to be easily composable in SysGen. A mixed number representation is used, and we adopt the precision used in [5].…”
We present a scalable design for accelerating the problem of solving a dense linear system of equations using LU Decomposition. A novel systolic array architecture that can be used as a building block in scientific applications is described and prototyped on a Xilinx Virtex 6 FPGA. This solver has a throughput of around 3.2 million linear systems per second for matrices of size N=4 and around 80 thousand linear systems per second for matrices of size N=16. In comparison with similar work, our design offers up to a 12-fold improvement in speed whilst requiring up to 50% less hardware resources. As a result, a linear system of size N=64 can be implemented on a single FPGA, whereas previous work was limited to a size of N=12 and resorted to complex multi-FPGA architectures to scale. Finally, the scalable design can be adapted to different sized problems with minimum effort.
“…Compared with [5], our TSA-based linear solver is ∼ 12× faster though no resource consumption results are available for comparison of area. From the power consumption perspective, actual processing utilization for our TSA-based SA design is low when compared to a 1D SA design.…”
Section: B Implementation Resultsmentioning
confidence: 99%
“…Our proposed design implements signed fixed-point number format with 9 integer bits and 8 binary bits, similar to [5], however our design differs in being wordlength and matrix size parameterizable at the PE level within the SA architecture. We make use of the DSP Blocks' dynamic configurability [6] to support multiple operations on the same hardware in different steps.…”
Section: A System Setupmentioning
confidence: 99%
“…The individual blocks are designed to be easily composable in SysGen. A mixed number representation is used, and we adopt the precision used in [5].…”
We present a scalable design for accelerating the problem of solving a dense linear system of equations using LU Decomposition. A novel systolic array architecture that can be used as a building block in scientific applications is described and prototyped on a Xilinx Virtex 6 FPGA. This solver has a throughput of around 3.2 million linear systems per second for matrices of size N=4 and around 80 thousand linear systems per second for matrices of size N=16. In comparison with similar work, our design offers up to a 12-fold improvement in speed whilst requiring up to 50% less hardware resources. As a result, a linear system of size N=64 can be implemented on a single FPGA, whereas previous work was limited to a size of N=12 and resorted to complex multi-FPGA architectures to scale. Finally, the scalable design can be adapted to different sized problems with minimum effort.
“…Whilst [14] presents a full fixed-point implementation, no analysis or guarantees are provided for handling the large dynamic range manifested in interior-point methods. Recently, activeset [18] and interior-point [16], [19] architectures were proposed using (very) reduced precision floating-point arithmetic and solving a condensed QP. Feasibility was demonstrated on an experimental setup with a 14th order SISO open-loop stable vibrating beam, with impressive computation times.…”
Abstract-Alternative and more efficient computational methods can extend the applicability of MPC to systems with tight real-time requirements. This paper presents a "system-on-a-chip" MPC system, implemented on a field programmable gate array (FPGA), consisting of a sparse structure-exploiting primal dual interior point (PDIP) QP solver for MPC reference tracking and a fast gradient QP solver for steady-state target calculation. A parallel reduced precision iterative solver is used to accelerate the solution of the set of linear equations forming the computational bottleneck of the PDIP algorithm. A numerical study of the effect of reducing the number of iterations highlights the effectiveness of the approach. The system is demonstrated with an FPGA-inthe-loop testbench controlling a nonlinear simulation of a large airliner. This study considers many more manipulated inputs than any previous FPGA-based MPC implementation to date, yet the implementation comfortably fits into a mid-range FPGA, and the controller compares well in terms of solution quality and latency to state-of-the-art QP solvers running on a standard PC.
“…This issue becomes particularly important when one tries to implement MPC on special purpose hardware, such as FPGA's [21,28], PLC's [32,19,45] or PAC's [18]. For these devices, linear MPC is demanding, as they have limited memory space and very low processing power.…”
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