Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers

Abstract

Abstract-Misalignment of delay-locked loop (DLL) output edges creates an undesired periodicity, resulting in reference harmonic tones at the output spectrum of edge-combining DLL (ECDLL)-based frequency synthesizers. These spurious tones corrupt the spectral purity to an unacceptable level for wireless applications. The spur magnitude is a random variable defined by the reference frequency, number of DLL phases, harmonic order, stage-delay standard deviation (SD), duty cycle distortion (DCD) of the reference clock, and static phase error (SPE) of the lockedloop due to charge pump/phase detector imperfections. Hence, to estimate the spurious performance of such synthesizers, exhaustive Monte Carlo (MC) simulations are inevitable. Based on closed-form expressions, this paper proposes a generic predictive model for harmonic spur characterization of ECDLLbased frequency synthesizers, whose prediction accuracy is independent of synthesizer design parameters and system nonidealities. Therefore, it can replace MC method to significantly accelerate the iterative design procedure of the synthesizer, while providing comparable predictions in terms of robustness and accuracy to that of MC. Validity, accuracy, and robustness of the proposed prediction method against wide-range values of nonidealities are verified through MC simulations of both the behavioral model and transistor-level model of the synthesizer in a standard 65-nm CMOS technology.Index Terms-delay mismatch, DLL, duty cycle distortion, frequency synthesizer, harmonic spur, Monte Carlo, periodic jitter, predictive model, static phase error

Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

“…To obtain a n variance, (E[a n ]) 2 and E[a n 2 ] are required. The former is determined directly from (6.15).…”

“…The latter is derived by calculating a n 2 from (6.13) and applying the expectation function. Next, the calculated (E[a n ]) 2 and E[a n 2 ] are substituted to the variance formula of (6.2) to find a n variance. This can be similarly done for b n .…”

“…Chapter 6 covers Paper 1 and Paper 2 [1], [2] and presents the development of a prediction model for estimation of spurious performance in edge-combining DLL-based synthesizers. In order to develop the model, the introduced analytical model in Chapter 5 is further expanded using Taylor series approximations and moment methods, and closed-form expressions are obtained for the probability density function (PDF) and mean value of the harmonic spur magnitudes.…”

“…Chapter 7 is based on Paper 1 and Paper 2 [1], [2] and discusses the development of a spur-aware MC-free design flow for DLL-based synthesizers. It replaces the standard flow which is based on an iterative circuit-level modification-and-simulation approach.…”

“…This chapter is based [1] and [2], and presents the development of a prediction model for the harmonic spur levels in edge-combining DLL-based frequency synthesizers. This model can replace the MC method to significantly speed up the iterative design procedure of such synthesizers, while providing predictions which are comparable in terms of robustness and accuracy to that of the MC method.…”