IMPLEMENTATIONS OF MONOLITHIC decision circuits for multigigabit communication systems have been based, in the main, on GaAs technology"'. Recently, a silicon decision circuit using a 0.5p bipolar process3 was reported. This paper will describe a monolithic silicon bipolar decision circuit using rather conventional 2.5p emitter stripe widths and pn-junction isolation, that may be extended into the multigigabit/ second range4. The architecture, implementation and experimental results will be covered.The common approach to a decision circuit is a masterslave D-flip flop. Commercially available silicon D-flip flops can be operated, at best, up to lGh/s. This range has now been extended to 1 .5Gb/s5. The bit rate can be increased by parallel operation4. The proposed decision circuit consists mainly of two identical flip flops, as illustrated in the functional block and the circuit diagrams. of Figure l a and b. The upper and the lower flip flops are operated in a complementary mode. They are enabled alternately by current switches in a series-gating configuration controlled by a sinusoidal clock. This mode of operation results in a demultiplexing of the input signal into two bit streams at half the bit rate, shifted in phase by half a clock cycle. A 2:l-multiplexer interleaves the two bit streams into one signal of the full bit rate. Thus, critical master-slave D-flip flop operation is required at only half the clock frequency for each bit stream.The chip dimensions are about 1.7 x 1.3mm2 and the total power dissipation is about 600mW at a supply voltage of -5V. The circuit was fabricated with a relatively conventional silicon bipolar technology which was also used for implementing a 2Gbjs 4: 1-multiplexer (MUX)6 and the master-slave D-flip flop'. The technology is characterized by 2.5p emitter stripe width,
