Monolithic CMUT-on-CMOS Integration for Intravascular Ultrasound Applications

Abstract

One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter based volumetric imaging arrays where the elements need to be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom designed CMOS receiver electronics from a commercial IC foundry. The CMUT on CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT to CMOS interconnection. This CMUT to CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire bonding method. Characterization experiments indicate that the CMUT on CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Experiments on a 1.6 mm diameter dual-ring CMUT array with a 15 MHz center frequency show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging CTOs located 1 cm away from the CMUT array.

CMUT-based volumetric ultrasonic imaging array design for forward looking ICE and IVUS applications

“…All IC's in single-chip system are custom design which includes pulsers, capable of generating 25-V unipolar pulses and low-noise receiver transimpedance amplifiers (TIAs) for each of the CMUT receive array elements. We have demonstrated the characterization and imaging performance of these devices in various studies [1][2][3][4]. In this study, ICE configuration (2.1-mm diameter array) is considered as a test case to explore the available design space offered by the CMUT-on-CMOS approach.…”

A Column-Row-Parallel ASIC architecture for 3D wearable / portable medical ultrasonic imaging

“…The CMUT technology offers advantages such as improved bandwidth, ease of fabricating large arrays, and potential for integration with electronics with the through-silicon vias (TSVs) [40,42,43] or monolithic CMUT-CMOS integration [44][45][46].…”

Characterization of improved Capacitive Micromachined Ultrasonic Transducers (CMUTS) using ALD high-Κ dielectric isolation

“…It is important to achieve the same full gap swing with a smaller amplitude voltage especially in the case of CMUT-on-CMOS integration applications when pulse amplitudes generated by IC are limited by the CMOS fabrication process [4]. To assess the improvement in electrostatic force generation by using HfO 2 instead of Si 3 N 4 isolation, the ratio of electrostatic force (R) generated by each device to that of an ideal parallel plate model with no isolation layer (1) for the same input voltage is defined as a figure of merit.…”