Monolithic 3D CMOS Using Layered Semiconductors

Abstract

Monolithic 3D integrated circuits using transition metal dichalcogenide materials and low-temperature processing are reported. A variety of digital and analog circuits are implemented on two sequentially integrated layers of devices. Inverter circuit operation at an ultralow supply voltage of 150 mV is achieved, paving the way to high-density, ultralow-voltage, and ultralow-power applications.

Bending induced electrical response variations in ultra-thin flexible chips and device modeling

“…Some of ultra-thin CMOS inverters reported in the literature are summarized in Table VI. 186,[188][189][190][191] Only few of them have investigated the effect of bending stress on the performance. The performance of the thinned Si CMOS inverter circuit by Kino et al 191 degrades under bending stress, as shown in Fig.…”

Synergetic photoluminescence enhancement of monolayer MoS2via surface plasmon resonance and defect repair

“…[1][2][3][4][5] An intrinsic difference of monolayer TMDCs from graphene is the direct bandgap (such as the MoS 2 monolayer with a bandgap of about 1.9 eV (ref. 6 and 7)), which enables these materials to have potential applications not only in eld-effect transistors (FETs), [8][9][10][11] but also in future optoelectronics (such as photodetectors and phototransistors).…”

Effect of Perforation on the Thermal and Electrical Breakdown of Self‐Rolled‐Up Nanomembrane Structures

“…[1][2][3][4][5][6][7][8][9][10][11] Strain-induced Self-Rolled-up Membranes (S-RuM) are of great interest due to their CMOS-compatible planar fabrication process and versatile 3D architectures produced by selfassembly. [1][2][3][4][5][6][7][8][9][10][11] Strain-induced Self-Rolled-up Membranes (S-RuM) are of great interest due to their CMOS-compatible planar fabrication process and versatile 3D architectures produced by selfassembly.…”