Monocrystalline Si membranes for pressure sensors fabricated by a novel surface micromachining process using porous silicon

Artmann, H.; Schaefer, Frank; Lammel, Gerhard; Armbruster, S.; Benzel, H.; Schelling, Christoph; Weber, Heribert; Vossenberg, Heinz-Georg; Gampp, R.; Muchow, Joerg; Laermer, Franz; Finkbeiner, S.

doi:10.1117/12.479564

Cited by 9 publications

(2 citation statements)

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“…Examples of MEMS-first processing schemes are illustrated in Figure 6 and 7. Figure 6 illustrates the advanced porous silicon membrane process developed by Robert Bosch GmbH, Stuttgart, Germany, which is an innovative method for manufacturing vacuum cavities sealed with monocrystalline silicon membranes in silicon wafers [64][65][66][67] . In this process, localized porous silicon is created via anodic etching in hydrofluoric acid (HF).…”

Section: Monolithic Mems and Ic Integration Using Mems-first Processingmentioning

confidence: 99%

Integrating MEMS and ICs

et al. 2015

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The majority of microelectromechanical system (MEMS) devices must be combined with integrated circuits (ICs) for operation in larger electronic systems. While MEMS transducers sense or control physical, optical or chemical quantities, ICs typically provide functionalities related to the signals of these transducers, such as analog-to-digital conversion, amplification, filtering and information processing as well as communication between the MEMS transducer and the outside world. Thus, the vast majority of commercial MEMS products, such as accelerometers, gyroscopes and micro-mirror arrays, are integrated and packaged together with ICs. There are a variety of possible methods of integrating and packaging MEMS and IC components, and the technology of choice strongly depends on the device, the field of application and the commercial requirements. In this review paper, traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed. These include approaches based on the hybrid integration of multiple chips (multi-chip solutions) as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques. These are important technological building blocks for the 'More-ThanMoore' paradigm described in the International Technology Roadmap for Semiconductors. In this paper, the various approaches are categorized in a coherent manner, their merits are discussed, and suitable application areas and implementations are critically investigated. The implications of the different MEMS and IC integration approaches for packaging, testing and final system costs are reviewed.

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Section: Monolithic Mems and Ic Integration Using Mems-first Processingmentioning

confidence: 99%

Integrating MEMS and ICs

et al. 2015

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“…Sintering means that the porous silicon, having a very large surface area, transforms into a material composition of single-crystalline silicon with embedded micro/nano cavities featuring minimum integral surface area. Those micro/nano cavities can be isolated or merged, depending on the porosity of the layer [8], [9], [10], [7]. As a result, the fine porous layer transforms into micro/nano cavity-rich single-crystalline silicon, while the coarse porous layer converts to a ~200 nm narrow, continuous cavity ( Fig.…”

Section: A Details Of the Chipfilm™ Pre-process Modulementioning

confidence: 99%

Technology and design aspects of ultra-thin silicon chips for bendable electronics

Richter

Rempp

Hassan

et al. 2009

2009 IEEE International Conference on IC Design and Technology

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Plastic electronics, thin-film-transistors on foil and ultra-thin chips on foil are technologies currently pursued to support the strongly emerging market for flexible electronics. Ultra-thin CMOS chips in such systems will provide solutions whenever high circuit performance and/or complexity are required.Ultra-thin Si chips (6 to 20 ȝm) are fabricated by using a recently introduced technology based on the pre/post-process modules Chipfilm™ and PickCrack&Place™ combined with a standard CMOS process. Prior to CMOS processing 200nm cavities are formed beneath the chip surface. The silicon quality is very comparable to that of bulk control wafers leading to similar process parameters and parameter variations.Fully operational digital and mixed-signal circuits having 30k and 38k/2.7k digital/analog CMOS transistors, respectively, are built on ultra-thin silicon chips by using an in-house CMOS gate array technology.The issue of piezoresistive effects in MOS transistors is studied on test transistors and small test circuits, where mechanical stress was introduced by bending a system of chip mounted on 50-μm Kapton foil. The results are compared to bulk silicon measurements. In addition, effects to circuit design, particularly on parametric yield, are deduced.The Chipfilm™ technology not only offers ultra-thin CMOS chips for electronic foil systems but can also be exploited for 3D circuit integration.

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