Monitoring the degradation that causes the breakdown of ultrathin (&lt;5 nm) SiO&lt;sub&gt;2&lt;/sub&gt; gate oxides

Rodrı́guez, R.; Miranda, E.; Pau, Riccardo; Suñé, J.; Nafría, M.; Aymerich, X.

doi:10.1109/55.841312

Cited by 23 publications

(10 citation statements)

References 8 publications

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“…9, it can be seen that the SILC tends to saturate at long times, i.e., the increase in SILC becomes sublinear in time for low voltage. A tendency for SILC to exhibit a saturating behavior at low stress voltage has been reported previously [44], [105]. In spite of this tendency, the ultrathin oxide samples stressed at lower voltage reach a higher average value of before breakdown.…”

Section: The Critical Defect Densitymentioning

confidence: 53%

“…If the low-fluence background is subtracted, a linear behavior is found independendent of stress conditions. At higher fluence (near breakdown) the saturation may be due to measurement technique, and the underlying defect generation probably continues in proportion to the fluence [105]. )…”

Section: The Critical Defect Densitymentioning

confidence: 99%

“…The critical defect density was taken as the value of immediately prior to the first soft or hard breakdown. However, for high fluence (i.e., near breakdown) and especially for low stress voltages, the SILC tends to saturate with increasing stress duration [44], [105]. This may limit the usefulness of SILC as a direct measure of .…”

Section: The Critical Defect Densitymentioning

confidence: 99%

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Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Stathis

2001

IEEE Trans. Device Mater. Relib.

163

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Abstract-The microelectronics industry owes its considerable success largely to the existence of the thermal oxide of silicon. However, recently there is concern that the reliability of ultra-thin dielectrics will limit further scaling to slightly thinner than 2 nm. This paper will review the physics and statistics of dielectric wearout and breakdown in ultrathin SiO 2 -based gate dielectrics. Electrons or holes tunneling through the gate oxide generate defects until a critical density is reached and the oxide breaks down. The critical defect density is explained by the formation of a percolation path of defects across the oxide. Only 1% of these paths ultimately lead to destructive breakdown, and the microscopic nature of these defects is not known. The rate of defect generation decreases approximately exponentially with supply voltage, below a threshold voltage of about 5 V for hot electron-induced hydrogen release. However, the tunnel current also increases exponentially with decreasing oxide thickness, leading to a decreasing time-to-breakdown and a diminishing margin for reliability as device dimensions are scaled. Estimating the reliability of the dielectric requires an extrapolation from the measurement conditions (e.g., higher voltage) to operation conditions. Because of the diminished reliability margin, it has become imperative to try to reduce the error in this extrapolation.Long-term ( 1 year) stress experiments are now being used to measure the wearout and breakdown of ultrathin ( 2 nm) dielectric films as close as possible to operating conditions. These measurements have revealed the details of the voltage dependence of the defect generation rate and critical defect density, allowing better modeling of the voltage dependence of the time-to-breakdown. Such measurements are used to guide the technology development prior to the manufacturing stage. We then discuss the nature of the electrical conduction through a breakdown spot and the effect of the oxide breakdown on device and circuit performance. In some cases, an oxide breakdown does not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.

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Section: The Critical Defect Densitymentioning

confidence: 53%

Section: The Critical Defect Densitymentioning

confidence: 99%

Section: The Critical Defect Densitymentioning

confidence: 99%

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Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Stathis

2001

IEEE Trans. Device Mater. Relib.

163

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“…To measure the SILC induced by CCS, the stress was periodically stopped after 100sec to measure the leakage current at, E ox = 1MV/cm of Al/Y 2 O 3 /Ge and Al/HfYO x /Ge structures shown in Figure 6(a) is plotted as a function of stress time. Under substrate hole injection (negative bias at gate) (-25mA/cm 2 ) SILC was gradually increase without showing a clear saturation which is due to generated defects during the stress [24]. SILC generation was found lower in case of HfYO x /Ge.…”

Section: Electrical Characterizationmentioning

confidence: 94%

Interface Structure and Charge Trapping in Hf-Incorporated Y₂O₃ Gate Dielectrics on Germanium

et al. 2011

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Y2O3 and HfYOx (~12nm) high dielectric constant films, with RF sputtering, have been prepared and studied with respect to their chemical bonding and electrical properties. The rapid thermal annealing after high-k dielectric deposition in N2 ambient showed major impacts on crystalinity properties. The incorporation of Hf into Y2O3 causes reduction in generation of positive oxide charge and leakage current density. The mechanism of leakage current reduction is considered to be due to Hf-induced compensation of existing oxygen vacancies. Moreover, HfYOx films exhibit superior electrical performances in terms of charge trapping induced flatband voltage instability and gate leakage current compared to directly deposited Y2O3 high-k dielectric films on Germanium. The density of interface traps (Dit) and border traps (Nbt) estimated from high-frequency CV curves (1 MHz) indicates that incorporation of Hafnium can improve the interfacial defects.The breakdown field in MIS capacitor with Y2O3 gate dielectric was significantly enhanced by incorporating Hf.

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“…The anode electric field increases with the continuous accumulation of trapped electrons. When the electric field reaches a certain critical value, destructive breakdown occurs and gate current has a sharp increase [14][15][16][17][18][19][20][21][22][23].…”

Section: Advances In Condensed Matter Physicsmentioning

confidence: 99%

The TDDB Characteristics of Ultra-Thin Gate Oxide MOS Capacitors under Constant Voltage Stress and Substrate Hot-Carrier Injection

Jia

Tan

Jiang

et al. 2018

Advances in Condensed Matter Physics

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The breakdown characteristics of ultra-thin gate oxide MOS capacitors fabricated in 65 nm CMOS technology under constant voltage stress and substrate hot-carrier injection are investigated. Compared to normal thick gate oxide, the degradation mechanism of time-dependent dielectric breakdown (TDDB) of ultra-thin gate oxide is found to be different. It is found that the gate current ( ) of ultra-thin gate oxide MOS capacitor is more likely to be induced not only by Fowler-Nordheim (F-N) tunneling electrons, but also by electrons surmounting barrier and penetrating electrons in the condition of constant voltage stress. Moreover it is shown that the time to breakdown ( bd ) under substrate hot-carrier injection is far less than that under constant voltage stress when the failure criterion is defined as a hard breakdown according to the experimental results. The TDDB mechanism of ultra-thin gate oxide will be detailed. The differences in TDDB characteristics of MOS capacitors induced by constant voltage stress and substrate hot-carrier injection will be also discussed.

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Monitoring the degradation that causes the breakdown of ultrathin (<5 nm) SiO<sub>2</sub> gate oxides

Cited by 23 publications

References 8 publications

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Interface Structure and Charge Trapping in Hf-Incorporated Y₂O₃ Gate Dielectrics on Germanium

The TDDB Characteristics of Ultra-Thin Gate Oxide MOS Capacitors under Constant Voltage Stress and Substrate Hot-Carrier Injection

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Monitoring the degradation that causes the breakdown of ultrathin (<5 nm) SiO<sub>2</sub> gate oxides

Cited by 23 publications

References 8 publications

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Interface Structure and Charge Trapping in Hf-Incorporated Y2O3 Gate Dielectrics on Germanium

The TDDB Characteristics of Ultra-Thin Gate Oxide MOS Capacitors under Constant Voltage Stress and Substrate Hot-Carrier Injection

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Product

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Interface Structure and Charge Trapping in Hf-Incorporated Y₂O₃ Gate Dielectrics on Germanium