MoM - a process variation aware statistical capacitance extractor

Ananthakrishna, R.; Batterywala, S.H.

doi:10.1109/vlsid.2006.119

Cited by 2 publications

(1 citation statement)

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“…In the interconnect geometries, the typical variations take account of linewidth, thickness, height, and interlayer dielectric thickness, and these variations can lead to substantial disagreement between the conceptual design and real fabricated chip. These discrepancies are collectively referred to as process variations [5]. Traditionally in the earlier technologies, designers were principally concerned with transistor variations, which could be captured by worst/best case process corners because a small number of process parameters, such as channel length, directly determined performance.…”

Section: Introductionmentioning

confidence: 99%

Extracting interconnect capacitance sensitivity to linewidth variation

Huang

Labun

2009

2009 Canadian Conference on Electrical and Computer Engineering

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VLSI interconnect capacitance is becoming more significant and also increasingly subject to process variation. A simple technique to extract from layout the sensitivity of interconnect parasitic capacitance to linewidth process variations is proposed based on 2.5D capacitance models and implemented in the Magic VLSI layout editor. The derivative of each extracted capacitance with respect to variation in every level is obtained. Coincident edges in layout result in distinct "shrinking" and "bloating" derivatives. The derivatives form a gradient that may be multiplied by a vector of the variations on each level to give the total expected deviation from nominal capacitance. The gradient allows the process sensitivity of each capacitance to be determined by simply inspecting the netlist.

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Section: Introductionmentioning

confidence: 99%