Extracting interconnect capacitance sensitivity to linewidth variation

Huang, Nick K. H.; Labun, A. H.

doi:10.1109/ccece.2009.5090117

Cited by 1 publication

(2 citation statements)

References 9 publications

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“…Since systematic variations are pattern dependent, parasitic capacitance extraction tools usually model their effects using sensitivity formulas as in [13]- [15]. Such a modeling approach has three main problems that impact the extraction accuracy: 1-it neglects the cross-dependency impact among different variation parameters on parasitic capacitances, 2-it uses a limited number of patterns and parameters to model the impact of systematic variations on parasitic capacitances, and 3-it has a high potential of pattern mismatches similar to the case of capacitance calculations (i.e., formulas).…”

Section: B Systematic Process Variationsmentioning

confidence: 99%

“…The current rule-based extraction tools handle the impact of systematic process variations on parasitic capacitances independently using sensitivity formulas that represent the sensitivity of a certain capacitance component to a certain variation parameter. Such formulas are pre-characterized with limited geometrical parameters [13]- [15]. Therefore, they also suffer from potential pattern mismatch and limited pattern coverage problems.…”

Section: Introductionmentioning

confidence: 99%

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Fast and Accurate Machine Learning Compact Models for Interconnect Parasitic Capacitances Considering Systematic Process Variations

Abouelyazid

Hammouda²,

Ismail

2022

IEEE Access

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A novel modeling methodology is developed for interconnect parasitic capacitances in rule-based extraction tools. Traditional rule-based extraction tools rely on pattern matching operations to match every interconnect structure with corresponding pre-characterized capacitance formulas. Such a method suffers from three main problems including limited pattern coverages, potential pattern mismatches, and limited handling of systematic process variations. These problems prohibit rule-based methods from coping with the new capacitance extraction accuracy requirements in advanced process nodes. The proposed methodology overcomes these problems by providing machine learning compact models for interconnect parasitic capacitances that cover varieties of realistic cross-section metal patterns. Those models efficiently include the impact of systematic process variations on parasitic capacitances. Moreover, each model can handle thousands of patterns replacing thousands of existing capacitance formulas. The input to the models is a cross-section pattern that is represented by a novel vertex-based pattern representation. The models are implemented using two different machine learning methods: neural networks and support vector regressions. The two methods are tested and compared to each other. The proposed methodology is tested over thirteen test chips of 28nm, 14nm, and 7nm process nodes with more than 6.7M interconnect cross-section patterns. The results show that the proposed methodology provided outstanding accuracy as compared to field-solvers and rule-based models with an average error < 0.15% and a standard deviation < 3.3%, whereas the average errors and standard deviations of rule-based models exceed 6%, for the same test chips. Also, the computational runtimes of the compact models are almost 2.5X faster than rule-based models.

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Section: B Systematic Process Variationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%