Fast and Accurate Machine Learning Compact Models for Interconnect Parasitic Capacitances Considering Systematic Process Variations

Abstract

A novel modeling methodology is developed for interconnect parasitic capacitances in rule-based extraction tools. Traditional rule-based extraction tools rely on pattern matching operations to match every interconnect structure with corresponding pre-characterized capacitance formulas. Such a method suffers from three main problems including limited pattern coverages, potential pattern mismatches, and limited handling of systematic process variations. These problems prohibit rule-based methods from coping with the new capacitance extraction accuracy requirements in advanced process nodes. The proposed methodology overcomes these problems by providing machine learning compact models for interconnect parasitic capacitances that cover varieties of realistic cross-section metal patterns. Those models efficiently include the impact of systematic process variations on parasitic capacitances. Moreover, each model can handle thousands of patterns replacing thousands of existing capacitance formulas. The input to the models is a cross-section pattern that is represented by a novel vertex-based pattern representation. The models are implemented using two different machine learning methods: neural networks and support vector regressions. The two methods are tested and compared to each other. The proposed methodology is tested over thirteen test chips of 28nm, 14nm, and 7nm process nodes with more than 6.7M interconnect cross-section patterns. The results show that the proposed methodology provided outstanding accuracy as compared to field-solvers and rule-based models with an average error < 0.15% and a standard deviation < 3.3%, whereas the average errors and standard deviations of rule-based models exceed 6%, for the same test chips. Also, the computational runtimes of the compact models are almost 2.5X faster than rule-based models.

RC Parasitic-Aware Layout Analysis and Routing Optimization Methodology

“…This method has three main problems. First, it uses simplified parasitic formulas that cannot cope with the new accuracy requirements of advanced process nodes [18], [19]. Second, this method does not deal with the parasitic effects as dominant factors on a circuit's performance.…”

“…First, some approaches use simplified parasitic models to speed up the extraction process and reduce the parasitic network such as in [12]- [14]. This approach is not efficient in advanced process technology nodes as it handles the parasitic effects as second order effects ignoring that the interconnect parasitic effects became one of the dominant factors on a circuit's performance in such advanced nodes [18], [19], [34]. Second, other approaches may use an incremental parasitic extraction to limit the parasitic extraction process to the modified polygons in a given layout.…”

“…Then, an electrostatic simulator is used to extract the lateral coupling capacitance between the two polygons accurately. Also, the simulator performs a parametric sweep over lateral spacings while it measures the coupling capacitance between the two metal polygons until the MR is achieved, given that the MR represents the distance where the coupling capacitance between the two polygons is less than or equal to 1% of the total capacitance on one of the polygons as shown in Figure 5 [18], [19].…”

“…In [18] and [19], the MR is used in a full layout parasitic capacitance extraction to identify the maximum coupling interaction distance for each metal polygon; however, in this work, the MR is used in an incremental parasitic capacitance extraction to identify the capacitance elements that are impacted by layout modifications, given that such impacted capacitance elements do not necessarily have direct coupling interactions with any modified metal polygon.…”

“…Many efforts were done to provide parasitic-aware routing optimization methods; however, they use either simplified parasitic models such as in [5], [9]- [14], or a full layout parasitic extraction such as in [15]- [17] to extract the parasitic elements of a layout design during the optimization processes. As for the methods that use simplified parasitic models, they provide a faster layout routing optimization; however, they are less accurate, and their parasitic extraction accuracy cannot cope with the accuracy requirements of advanced process nodes [18], [19]. On the other hand, the methods that use a full layout parasitic extraction provide more accurate layout optimization; however, they are very slow as they require a full layout parasitic extraction with every iteration in the optimization loop.…”