Molecular beam epitaxial growth and structural properties of HgCdTe layers on CdTe(211)B/Si(211) substrates

Yang, Bin; Xin, Yan; Rujirawat, Saroj; Browning, Nigel D.; Sivananthan, S.

doi:10.1063/1.373631

Cited by 14 publications

(10 citation statements)

References 10 publications

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“…Many types of structural defects have been reported in epitaxially grown HgCdTe alloys, including misfit dislocations [25,26], threading dislocations [25][26][27], stacking faults and twins [26][27][28][29][30], cross-hatch defects [31,32], surface crater defects [28,[33][34][35][36][37][38][39][40][41][42], and pyramidal hillocks [25,29], as well as precipitates [8,43]. Here, electron microscopy studies of these various growth defects are discussed and illustrated.…”

Section: Defects In Hgcdte Epilayersmentioning

confidence: 98%

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Defect characterization for epitaxial HgCdTe alloys by electron microscopy

Aoki

Chang

Badano

et al. 2004

Journal of Crystal Growth

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Section: Defects In Hgcdte Epilayersmentioning

confidence: 98%

“…Twinning is the most common type of growth defect occurring in HgCdTe and CdTe alloys [26][27][28][29][30]. Thus, avoiding twin formation is an important issue for overall improvement of HgCdTe quality.…”

Section: Twin Formationmentioning

confidence: 99%

Defect characterization for epitaxial HgCdTe alloys by electron microscopy

Aoki

Chang

Badano

et al. 2004

Journal of Crystal Growth

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“…For operation at 78 K, 5 9 10 5 cm À2 is a good target EPD. 2 The achievement of this final device EPD would require the substrate to have an even lower EPD, as the number of TDs increases inside the final MCT layer, 3 even when grown on lattice-matched substrates. To date, the best annealing strategies for CdTe/Si routinely attain the 10 6 cm À2 level, and densities as low as 5 9 10 5 cm À2 have been achieved.…”

Section: Introductionmentioning

confidence: 99%

Simulations of Dislocations in CdZnTe/SL/Si Substrates

Ciani

Chung

2009

Journal of Elec Materi

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Discrete dislocation dynamics simulations were employed to study the primary mechanisms by which superlattices (SLs) block threading dislocations (TDs) from reaching the surface of a composite CdZnTe/SL/Si substrate. We found that the difference in strain (composition) across layer boundaries played a key role as to whether a TD might veer away or continue across. We also found that, while the distance between interfaces had little effect on the motion of a single TD, it could have an impact on the dislocation tangle as a whole and should be considered carefully in SL design. We discuss our results in relation to the design of SLs for TD blocking. INTRODUCTIONLattice-matched substrates with large areas are required to obtain economy of scale for the production of high quality long wave infrared (LWIR) Hg 1Àx Cd x Te (MCT) based devices. The best candidate for this task is the composite CdTe/Si substrate; however, high threading dislocation (TD) densities (>10 6 cm À2 ) at the surfaces of CdTe/Si substrates prohibit their effective use for (LWIR) detectors. Johnson et al. 1 showed that R 0 A j (the resistance at zero-bias 9 the junction area) begins to plateau toward its highest value as the etch pit density (EPD) drops below 5 9 10 5 cm À2 . For operation at 78 K, 5 9 10 5 cm À2 is a good target EPD. 2 The achievement of this final device EPD would require the substrate to have an even lower EPD, as the number of TDs increases inside the final MCT layer, 3 even when grown on lattice-matched substrates. To date, the best annealing strategies for CdTe/Si routinely attain the 10 6 cm À2 level, and densities as low as 5 9 10 5 cm À2 have been achieved. 4 Superlattices (SLs) have been observed to block the rise of TDs, reducing the number reaching the free surface in both III-V 5-7 and II-VI 8-11 semiconductor materials, although their ability to do so varies. In some cases, an SL may even increase the number of dislocations. 7 There are a moderate number of adjustable parameters in SL construction, which may not be independent with respect to TD blocking. This leads to a large problem space over which to design and test SLs, while, at the same time, the rules for how each of these parameters might influence dislocation blocking are unclear.In this paper we present results of discrete dislocation dynamics (DDD) 12,13 simulations investigating strategies for dislocation blocking via variable SL periodicities. The number of equations that govern the dislocations, their mutual interactions, and interactions with surfaces and interfaces, is far too large to be tractable by hand. DDD provides a means by which the equations can be integrated numerically and enables SL design parameters to be investigated systematically. Although, by now, the general parameter space for SL layer growth and TD mechanisms are wellunderstood, qualitative rules that govern their intersection still remain largely uncertain. In this work we studied (1) how the individual layer thickness affects the ability of TDs to encounter the next layer, there...

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“…This orientation is of particular importance to CdTe and HgCdTe growth by MBE. [1][2][3][4][5][6] However, low-energy electron diffraction (LEED) investigations of stepped surfaces, such as (211), are a particularly difficult problem. The Si (211) surface has been investigated for over 20 years, but the conclusions 7-9 are inconsistent; specifically they do not agree with the results of recent scanning tunneling microscopy (STM) investigations [10][11][12][13][14][20][21][22] demonstrating the intractability of the problem.…”

Section: Introductionmentioning

confidence: 99%

The structure of the Si (211) surface

Fulk

Sivananthan

Zavitz

et al. 2006

Journal of Elec Materi

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Silicon (211) has been proposed as an alternative substrate for CdTe/HgCdTe molecular beam epitaxial growth. Silicon has a clear advantage over other substrates because of its low cost, high strength, and thermal-expansion coefficient, which matches that of the silicon readout integrated circuit. The (211) orientation has been shown to yield high-quality CdTe and HgCdTe/CdTe layers over other orientations. The reconstruction and faceting of the Si (211) surface is poorly understood despite the importance of the (211) orientation. The results of low-energy electron diffraction (LEED) studies have been contradictory, and their conclusions are inconsistent with recent scanning tunneling microscopy (STM) studies. LEED and STM images were used to determine the most probable Si (211) surface facet structure as a function of annealing temperature. Samples annealed at a high temperature (i.e., . 1260°C) allowed the formation of ordered LEED spot patterns as opposed to the typically reported ½ 111 streaks. The pattern in the ½0 11 direction gave a consistent 23 (7.68 Å ) reconstruction.

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Molecular beam epitaxial growth and structural properties of HgCdTe layers on CdTe(211)B/Si(211) substrates

Cited by 14 publications

References 10 publications

Defect characterization for epitaxial HgCdTe alloys by electron microscopy

Defect characterization for epitaxial HgCdTe alloys by electron microscopy

Simulations of Dislocations in CdZnTe/SL/Si Substrates

The structure of the Si (211) surface

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