Mold Fabrication for 3D Dual Damascene Imprinting

Abstract

Previously, a damascene process based on nanoimprint lithography has been proposed (Schmid G M, et al. in J Vac Sci Technol B 24(3) 1283, 2006) to greatly reduce the fabrication steps of metal interconnection in integrated circuit. For such a process to become a viable technique, a mold having two pattern levels with precise alignment between them must be fabricated first. To this end, this work demonstrates a “self-aligned” fabrication process where the two pattern levels would be perfectly aligned if ignoring the noise during e-beam writing. The process is based on one EBL on a bi-layer resist stack, with the sensitivity for the top layer much higher than that of the bottom layer, which enables separate pattern transfer of the two pattern levels. Using ZEP-520A and poly(dimethylglutarimide) (PMGI) resists, we fabricated pillars having a diameter of 150 nm sitting on ridges having a width of 1.5 μm, which can be used to create via-holes and trenches for IC interconnect by nanoimprint lithography. The current process can also find applications in other areas that require two-level patterning with precise alignment between them.

Influence of surface properties on the electrical conductivity of silicon nanomembranes

“…It is known that after dosing with hydrogen under vacuum, the surface is purely H-terminated [ 16 , 21 ], while after HF treatment and DI water rinse, the surface is H-terminated with trace amounts of OH and F [ 12 , 14 , 23 ]. Figure 3 shows XPS spectra of 220-nm SiNMs treated by the two surface modifications after 20-min exposure to air.…”

“…Silane in a H 2 carrier gas was then flowed across the sample for 30 s while it was maintained at 580°C and for an additional 2 min after turning off the heat source. It is known that this procedure produces a H-terminated surface [ 21 ], and indeed, the samples were hydrophobic after removing from vacuum.…”

Gadolinium oxide nanocrystal nonvolatile memory with HfO2/Al2O3 nanostructure tunneling layers

“…The lowest initial charge loss rate for DL_2 (5 nm) samples can be obtained since the physical thickness of the nanostructure tunneling layer is greater than that of the other samples. On the other hand, the initial charge loss rate of the sample with the Al 2 O 3 tunneling layer is higher not only due to the reduced physical thickness, but also due to the lower conduction band offset between Al 2 O 3 and Si [ 24 ]. In addition, the activation energy was extracted in order to understand the temperature dependence of the charge loss mechanism; this is shown in Figure 6b .…”

Mixture of ZEP and PMMA with varying ratios for tunable sensitivity as a lift-off resist with controllable undercut

“…Besides lift-off that is the subject of the present study, such a resist mixture having adjustable sensitivity can also be utilized to fabricate complicated quasi-3D structures mimicking Morpho butterfly scales using many layer resist film stacks, 13,22 or an imprint mold for a dual damascene process to fabricate Cu interconnect for integrated circuit. 23…”