Modular supervisory control of an experimental automated manufacturing system

Nourelfath, Mustapha; Niel, Éric

doi:10.1016/s0967-0661(03)00056-x

Cited by 36 publications

(18 citation statements)

References 25 publications

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“…Although several applications reported in the literature, e.g., [15,22,23], include implementation of synthesized supervisors on a PC or a PLC, they are usually put in practice in an academic setup. To our knowledge, the industrial applications described in [12,18,34] are ones of the few that actually refer to an existing industrial product.…”

Section: Industrial Casesmentioning

confidence: 99%

Integration of Supervisory Control Synthesis in Model-Based Systems Engineering

2016

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Increasing system complexity, time to market and development costs reduction place higher demands on engineering processes. Formal models play an important role here because they enable the use of various model-based analyses and early integration techniques and tools. Engineering processes based on formal models are able to cope with complexity. They also support time to market and development costs reduction. Moreover, application of supervisory control synthesis in the development of control systems can speed up the process considerably. This paper discusses the integration of recently developed supervisor synthesis techniques and tools in engineering processes. To illustrate this approach, examples of industrial cases are presented, where supervisors synthesized have successfully been implemented and integrated in existing resource control platforms. IntroductionIn current industrial practice, it is very difficult to deal with high-tech multidisciplinary system development due to system complexity, market pressure, and resource limitations. To overcome the difficulties, various kinds of models are used increasingly often in the development process. Specifically, formal and executable models built and employed in the design phase can be used to assess functional correctness and performance of component designs and overall system design. Formal verification, in particular model checking [3], is employed when a high degree of confidence in functional correctness of a design is required. To assess design performance, one

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Section: Industrial Casesmentioning

confidence: 99%

Integration of Supervisory Control Synthesis in Model-Based Systems Engineering

2016

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“…Such an interpretation can be direct (Nourelfath and Niel 2004) if the supervisor sequences contain at least one controllable event between two uncontrollable events. This means that the supervisor reacts to a given input by emitting an output before a new input occurs.…”

Section: Implementation Issuesmentioning

confidence: 99%

Supervisory synthesis for product-driven automation and its application to a flexible assembly cell

Pétin¹,

Gouyon²,

Morel³

2007

Control Engineering Practice

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“…Similarly, [18] also discusses translating DES into PLC programs. The difference is that they first convert automata into the Grafcet language, which describes the specification of logic controllers.…”

Section: Introductionmentioning

confidence: 99%

“…They then translate the Grafcet language into a PLC program. Both [12] and [18] uses automated manufacturing testbeds as examples.…”

Section: Introductionmentioning

confidence: 99%

Sampled-Data Supervisory Control

Leduc

Wang

2010

IFAC Proceedings Volumes

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This thesis focuses on issues related to implementing theoretical Discrete-Event Systems (DES) supervisors, and the concurrency and timing delay issues involved.Sampled-data (SD) supervisory control deals with timed DES (TDES) systems where the supervisors will be implemented as SD controllers. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes states, and updates its outputs.In this thesis, we identify a set of existing TDES properties that will be useful to our work, but not sufficient. We extend the TDES controllability definition to a new definition, SD controllability, which captures several new properties that will be useful in dealing with concurrency issues, as well as make it easier to translate a TDES supervisor into an SD controller.We then establish a formal representation of an SD controller as a Moore Finite State Machine (FSM), and describe how to translate a TDES supervisor to a FSM, as well as necessary properties to be able to do so. We discuss how to construct a single centralized controller, as well as a set of modular controllers and show that they will produce equivalent output.Next, we capture the enablement and forcing action of a translated controller in the form of a TDES supervisory control map, and show that the closed-loop behavior of this map and the plant is the same as that of the plant and the original TDES supervisor. We also show that our method is robust with respect to nonblocking and certain variations in the actual behavior of our physical system.We also introduce a set of predicate-based algorithms to verify the SD controllability property, as well as certain other conditions that we require. We have created a software tool for verifying these conditions and provide the source code in the appendix. We have implemented these algorithms using binary decision diagrams (BDD).For illustrative purpose, we have produced a set of examples which fail the key conditions discussed in this thesis, as well as a successful application example based on a Flexible Manufacturing System. We also presented the corresponding FSM, iii iv translated from the example's supervisors.

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Modular supervisory control of an experimental automated manufacturing system

Cited by 36 publications

References 25 publications

Integration of Supervisory Control Synthesis in Model-Based Systems Engineering

Integration of Supervisory Control Synthesis in Model-Based Systems Engineering

Supervisory synthesis for product-driven automation and its application to a flexible assembly cell

Sampled-Data Supervisory Control

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