Abstract-The setting of this paper is the implementation of timed discrete-event systems (TDES) as sampled-data (SD) controllers. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes states, and updates its outputs.In this paper, we establish a formal representation of an SD controller as a Moore synchronous finite state machine (FSM). We describe how to translate a TDES supervisor to a FSM, as well as necessary properties to be able to do so. We discuss how to construct a single centralized controller as well as a set of modular controllers, and show that they will produce equivalent output.We also discuss a flexible manufacturing system (FMS) example and present some FSM translation issues encountered, as well as the FSM version of some of the system's supervisors.
I. INTRODUCTION In the area of Discrete-Event Systems (DES) [1], [2], [3], a lot of effort has been devoted to studying standard properties such as nonblocking and controllability in a theoretical setting. However, limited effort has been made in investigating what an implementation of a DES supervisor would be like.A good implementation method for DES supervisors would be as sampled-data (SD) controllers. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge, it samples its inputs, changes state, and updates its outputs. An example of an SD controller might be a programmable logic controller (PLC) [4] or a Moore synchronous finite state machine (FSM) [5]. We are particularly interested in implementing timed DES (TDES) [6] as SD controllers.When we are using an SD controller to manage a given system, we associate an input with each event, and an output with each controllable event. We consider an event to have occurred when its corresponding input has gone true during a given clock period. We consider a controllable event to be enabled when its corresponding output has been set true by the controller, disabled otherwise. Finally, we associate the clock edge that drives the SD controller with the TDES tick (τ ) event.These definitions have several ramifications. First, an SD controller does not know an event has occurred until the next clock edge, and then it has no information on the order or number of occurrences of events. The only ordering information that remains is which sampling period (clock period) a given event occurred in.As an example, consider Fig. 1. We see on the third rising edge of the clock, the SD controller knows that both events e1 and e2 have occurred, but not which came first. This means that the SD controller can't tell the difference between the strings e1-e2-τ , e2-e1-τ , or e1-e2-e1-τ .
