Modular Routing Design for Chiplet-Based Systems

Yin, Jieming; Lin, Zhifeng; Kayıran, Onur; Poremba, Matthew; Altaf, Muhammad Shoaib Bin; Jerger, Natalie Enright; Loh, Gabriel H.

doi:10.1109/isca.2018.00066

Cited by 76 publications

(33 citation statements)

References 34 publications

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“…Since this paper refers to different hierarchy levels of communications, a different communication protocol should be designed in order to cover the communication between the NoC that is placed in the interposer and the NoC which is placed within the chiplets. A very nice routing composable, topology agnostic, deadlockfree routing methodology is presented on [26] that covers the whole chiplet-based system. We do believe that the integration of SDNoC approach in combination with the work proposed in [26] could be a strong contribution for future chiplet-based systems.…”

Section: Discussionmentioning

confidence: 99%

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MicroLET: A New SDNoC-Based Communication Protocol for ChipLET-Based Systems

Ellinidou

Sharma

Kontogiannis

et al. 2019

2019 22nd Euromicro Conference on Digital System Design (DSD)

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Currently the industry moves to smaller process nodes even if the cost for yielding large dies continues to increase, moving to the 5nm and even 3nm nodes. Hence a chipletbased design has been initiated and quickly gain attention from industry, academia and government agencies. This cutting edge approach became advantageous to break down a large die into smaller chiplets in order to improve yield and binning. In order to exploit this new approach the interconnect fabric connecting the nodes of the entire system should be of high importance to enable the properly distribution of the data. Each individual chiplet may contain its own local Network on Chip (NoC), which operates for intra-chiplet traffic. However the communication over chipletbased systems is complicated enough, due to various routing algorithms and NoC topologies and an alternative solution is needed. In this paper we introduce an SDNoC(Software Define Network on Chip)-based communication protocol for chipletbased systems, called MicroLET, which consists of a flexible and modular SDNoC architecture and 3 main phases: Handshake, Network Monitoring, Routing. An implementation of the SDNoC architecture and an evaluation of the proposed routing algorithm compared to the XY and the Odd-Even algorithms within different traffic scenarios is presented. Through the evaluation of the MicroLET protocol, it is proven that it could be a good candidate for the future chiplet-based systems.

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Section: Discussionmentioning

confidence: 99%

“…A very nice routing composable, topology agnostic, deadlockfree routing methodology is presented on [26] that covers the whole chiplet-based system. We do believe that the integration of SDNoC approach in combination with the work proposed in [26] could be a strong contribution for future chiplet-based systems.…”

Section: Discussionmentioning

confidence: 99%

MicroLET: A New SDNoC-Based Communication Protocol for ChipLET-Based Systems

Ellinidou

Sharma

Kontogiannis

et al. 2019

2019 22nd Euromicro Conference on Digital System Design (DSD)

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“…But instead of the event triggered model that Garnet utilizes in the full system simulator, we use the time triggered model, like BookSim [22], which is more suitable for the cycle-accurate simulation control and result collection. In the interconnect, we utilize the router with a two-stage pipeline (as in many state-of-the-art works such as [23] [24] [25]) as an example, and the transaction's transfer latencies in a router and a link are both 2 cycles. Each output port contains 2 virtual networks (VNs), separately utilized by the response and request transactions to avoid protocollevel deadlock in the real system.…”

Section: Experiments a Methodologymentioning

confidence: 99%

Efficient Support of AXI4 Transaction Ordering Requirements in Many-Core Architecture

Wang

2020

IEEE Access

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The Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface 4 (AXI4) protocol was initially a bus oriented interface designed for on-chip communication. To offer the possibility of utilizing the AXI4 based processors and peripherals in the on-chip network based system, we propose a whole system architecture solution to make the AXI4 protocol compatible with the Networkon-Chip (NoC) based communication interconnect in the many-core architecture. Due to the out-of-order transaction in the NoC interconnect, which conflicts with the ordering requirements specified by the AXI4 protocol, we especially focus on the design of the transaction ordering units, realizing a high-performance and low cost (area) solution to the ordering requirements by the sequence ID (seq_ID) reuse mechanism and a simple but smart seq_ID synchronization process. Besides, the micro-architectures and the functionalities of the transaction ordering units are described and explained in detail for ease of implementation. The experimental results in a C++ based system simulator show that, compared with the state-of-the-art works, our solution can maximally increase the system throughput by 66.0% and decrease the transaction queueing delay in the master-side ordering unit by 91.2%. INDEX TERMS AMBA AXI4, many-core architecture, Netowrk-on-Chip (NoC), ordering model.

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“…Looking forward, this trend will only increase; large-memory (1-100 TBs) machines are integrating even more devices with different performance characteristics like Intel's Optane memory [6]. Furthermore, emerging architectures using chiplets and multi-chip modules [17,33,44,45,48,54,65,67] will drive the multi-socket and NUMA paradigm: accessing memory attached to the local socket will have higher bandwidth and lower latency than accessing memory attached to a remote socket. Note that accessing remote memory can incur 2-4x higher latency than accessing local memory [1].…”

Section: Numa Architecturesmentioning

confidence: 99%

Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory Machines

Achermann

Panwar²,

Bhattacharjee

et al. 2020

Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Syste

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Multi-socket machines with 1-100 TBs of physical memory are becoming prevalent. Applications running on multi-socket machines suffer non-uniform bandwidth and latency when accessing physical memory. Decades of research have focused on data allocation and placement policies in NUMA settings, but there have been no studies on the question of how to place page-tables amongst sockets. We make the case for explicit page-table allocation policies and show that pagetable placement is becoming crucial to overall performance.We propose Mitosis to mitigate NUMA effects on page-table walks by transparently replicating and migrating page-tables across sockets without application changes. This reduces the frequency of accesses to remote NUMA nodes when performing page-table walks. Mitosis uses two components: (i) a mechanism to enable efficient page-table replication and migration; and (ii) policies for processes to efficiently manage and control page-table replication and migration.We implement Mitosis in Linux and evaluate its benefits on real hardware. Mitosis improves performance for large-scale multi-socket workloads by up to 1.34x by replicating pagetables across sockets. Moreover, it improves performance by up to 3.24x in cases when the OS migrates a process across sockets by enabling cross-socket page-table migration.

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Modular Routing Design for Chiplet-Based Systems

Cited by 76 publications

References 34 publications

MicroLET: A New SDNoC-Based Communication Protocol for ChipLET-Based Systems

MicroLET: A New SDNoC-Based Communication Protocol for ChipLET-Based Systems

Efficient Support of AXI4 Transaction Ordering Requirements in Many-Core Architecture

Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory Machines

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