Modular equivalence verification of polynomial datapaths with multiple word-length operands

Abstract

In this paper, we extend Modular Horner Expansion Diagram (Modular-HED) as a canonical polynomial representation to verify polynomial functions with multiple bit-width operands from nd n n Z Z Z 2 2 2 ... 2 1 × × to n Z 2 . Our contributions are mostly in efficient implementation of [1] with a canonical decision diagram in such a way that both verification and synthesis of large arithmetic circuits can be more efficient. The experimental results show the effectiveness of our approach in comparison with other decision diagrams and algebraic techniques.

A memory-efficient canonical data structure for decimal floating point arithmetic systems modeling and verification

“…Floating point modeling is still beyond the capabilities of the TED. Another representation trying to improve the performance of modeling is the Horner expansion diagram (HED) and its modular version, the M-HED [27,28]. These representations, though powerful, are not capable of modeling floating points.…”

Proof logging for computer algebra based SMT solving

“…This approach is efficient for arithmetic circuits with only word-level arithmetic constraints. There are also other approaches to represent computer algebra constraints with so called Horner Expansion Diagrams [13]. Also this approach is working on the word-level and can handle word-level arithmetic constraints only.…”