Modular Arithmetic CPM for SDR Platforms

Ramirez-Perez, Abisai; Aldana‐López, Rodrigo; Longoria-Gándara, O.; Valencia-Velasco, Jose; Pizano-Escalante, Luis; Parra-Michel, R.

doi:10.1109/tcsii.2022.3143762

Cited by 4 publications

(3 citation statements)

References 17 publications

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“…However, the quantization noise from computing the cumulated phase increases when the modulation indices do not have an exact representation in a given fixed-point format, e.g., h = 1 3 . To deal with this, modular arithmetic units are used to obtain the accurate signal computation for the CPM transmitter in [34]. Here, the modulation indices can be represented accurately in a given fixed-point format.…”

Section: Multi-h Cpm Transmitter Implementationmentioning

confidence: 99%

Design and Implementation of a Low-Complexity Multi-h CPM Receiver with Linear Phase Approximation Synchronization Algorithm

Wang,

Wen,

et al. 2023

Entropy

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Multi-h continuous phase modulation (CPM), with extremely high spectral efficiency, involves the plague of high demodulation complexity with a large number of matched filters and a complex trellis. In this paper, an efficient all-digital demodulator for multi-h continuous phase modulation (CPM) is proposed based on a low-complexity decision-directed synchronization algorithm. Based on the maximum-likelihood estimation of the carrier phase and timing errors, we propose a reduced-complexity timing error detector with linear phase approximation (LPA) to the phase of the multi-h CPM. Compared with the traditional synchronization methods, it avoids derivative matched filtering and reduces about 2/3 of matched filters. The estimated accuracy and bit error rate (BER) performance of the LPA-based synchronization algorithm have no loss, as shown by the numerical simulation. Its stability is verified by the derived S-curve. Then, the receivers with the LPA-based synchronization for the three kinds of promising multi-h CPM are implemented on a Xilinx Kintex-7 FPGA platform. The experimental results show that the onboard tested BER of the proposed design has an ignorable loss in the numerical simulation. The implementation overhead on FPGA is significantly reduced by about 27% slices, 64% DSPs, and 70% block RAMs compared with the conventional method.

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Section: Multi-h Cpm Transmitter Implementationmentioning

confidence: 99%

Design and Implementation of a Low-Complexity Multi-h CPM Receiver with Linear Phase Approximation Synchronization Algorithm

Wang,

Wen,

et al. 2023

Entropy

View full text Add to dashboard Cite

show abstract

“…However, the quantization noise from computing the cumulated phase increases when the modulation indices do not have an exact representation in a given fixed-point format, e.g., h = 1 3 . In order to deal with that, modular arithmetic units are used to obtain the accurate signal computation for the CPM transmitter in [27]. Here, the modulation indices can be represented accurately in a given fixed-point format.…”

Section: A Multi-h Cpm Transmitter Implementationmentioning

confidence: 99%

Design and implementation of coherent multi-h CPM receiver with low-complexity decision-directed synchronization algorithm

Wang¹

2022

Preprint

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<p> In this paper, an efficient all-digital demodulator for multi-h CPM is proposed based on a low-complexity decision-directed synchronization algorithm. We derive the maximum-likelihood estimation of the carrier phase and timing errors and propose a reduced-complexity timing error discriminator with the linear phase approximation (LPA). Compared to the traditional synchronization method, it reduces about 2/3 of matched filter banks since only on-time matched filter banks are required. To demonstrate the stability of the proposed algorithm, the S-curve is derived theoretically and plotted with numerical simulation. The numerical results show that the LPA-based synchronization algorithm has no loss of bit error rate (BER) performance compared to the commonly used methods. Then, the LPA-based synchronization and the maximum-likelihood sequence detection for the three kinds of promising multi-h CPM demodulation are implemented on a Xilinx Kirtex-7 FPGA platform achieving the global clock rate of 200MHz. The BER of the overall receiver is tested on board, and the results show that its performance has an ignorable loss to the numerical simulation. The implementation overhead on FPGA is reduced by about 30% compared to the conventional method. </p>

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“…It refers to radio communication in which the transmitter modulation is generated or defined by a software platform and the receiver uses also the same one to recover the signal intelligently. Recently, SDR implementation has been used in several research work because it provides performances improvement, flexibility and low cost [15][16][17][18][19]. Hence, various researches have been directed towards the exploitation of SDR technology for chaotic digital communications.…”

Section: Introductionmentioning

confidence: 99%

Experimental validation of new non-coherent chaotic modulation via SDR implementation

Benimam¹,

Sadoudi²,

Teguig³

2022

Phys. Scr.

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In this article, a new non-coherent chaotic modulation based on the classical Frequency Modulation (FM) technique is proposed and experimentally validated under realistic wireless communication scenarios by using Software Defined Radio (SDR) technology. In the proposed modulation, named FM-Chip Averaging Chaotic On-Off Keying (FM-CACOOK), we simply combine the FM modulation with the recent proposed chaotic modulation technique CA-COOK. Firstly, we validate the proposed technique via several Matlab simulations scenarios in the context of wireless chaotic transmission through different IEEE 802.15.4a channel models. In this context, we choose the Office LOS (Line Of Sight) and NLOS (Non Line Of Sight), the industrial LOS, the Outdoor LOS and the Open Outdoor NLOS in order to make a mixture of indoor and outdoor environments for LOS and NLOS propagation. Secondly, we implement the proposed modulation by using GNU-Radio Companion (GRC) software. For this, several new GRC blocks have been added to perform and test the FM-CACOOK modulation in SDR platforms such as RTL-SDR dongle and HackRF. Finally, experimental tests have been performed to demonstrate the reliability and the strengths of the considered modulation. The obtained experimental results validate our solution by deriving the Bit Error Rate (BER) performances curve of FM-CACOOK compared to that of Differential Chaos-Shift Keying (DCSK), which is the reference chaotic modulation, and to that of the recent CA-COOK modulation.

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Modular Arithmetic CPM for SDR Platforms

Cited by 4 publications

References 17 publications

Design and Implementation of a Low-Complexity Multi-h CPM Receiver with Linear Phase Approximation Synchronization Algorithm

Design and Implementation of a Low-Complexity Multi-h CPM Receiver with Linear Phase Approximation Synchronization Algorithm

Design and implementation of coherent multi-h CPM receiver with low-complexity decision-directed synchronization algorithm

Experimental validation of new non-coherent chaotic modulation via SDR implementation

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