Modified Montgomery modular multiplication and RSA exponentiation techniques

McIvor, C.; McLoone, M.; McCanny, J.V.

doi:10.1049/ip-cdt:20040791

Cited by 125 publications

(93 citation statements)

References 6 publications

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“…The cost of creating our puzzle is easier than Diffie-Hellman based scheme proposed by Waters and Juels [10], because modular multiplication is much quicker than modular exponentiation [27].…”

Section: Claim 2 a Defending Server Performs Two Modular Multiplicatimentioning

confidence: 99%

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Efficient Trapdoor-Based Client Puzzle Against DoS Attacks

Gao

Susilo²,

Mu³

et al. 2010

Network Security

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Denial of Service (DoS) attack is one of prevalent and mass-destructive threats to web servers, which aims at shutting down a target server by depleting its resource and obliging the victim incapable of offering stable and integrated service to legitimate clients. Client puzzle is proposed for a promising countermeasure against DoS attacks. In this paper, we propose a new trapdoor-based client puzzle to overcome most of the underlying drawbacks of the traditional ones. Our trapdoor-based client puzzle is provably secure.

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Section: Claim 2 a Defending Server Performs Two Modular Multiplicatimentioning

confidence: 99%

“…However, the cost for computing a puzzle on a defending server is still unsatisfactory. To obtain the solution a defending server has to perform one modular exponentiation, which is actually equivalent to a large number of modular multiplications [27].…”

Section: Related Workmentioning

confidence: 99%

Efficient Trapdoor-Based Client Puzzle Against DoS Attacks

Gao

Susilo²,

Mu³

et al. 2010

Network Security

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“…Thus, the ALU of a crypto-processor has been designed using reversible logic. As a prototype of applying reversible logic for designing the crypto-ALU, reversible designs of carry propagate adders and five-to-two CSA and four-to-two CSA adders [6] are presented. Figure 3 shows the reversible carry propagate adder using the TSG.…”

Section: Reversible Tsg Gate As Full Addermentioning

confidence: 99%

Reversible Logic to Cryptographic Hardware: A New Paradigm

Thapliyal

Zwoliński

2006

2006 49th IEEE International Midwest Symposium on Circuits and Systems

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Abstract-Differential Power Analysis (DPA) presents a major challenge to mathematically-secure cryptographic protocols. Attackers can break the encryption by measuring the energy consumed in the working digital circuit. To prevent this type of attack, this paper proposes the use of reversible logic for designing the ALU of a cryptosystem. Ideally, reversible circuits dissipate zero energy. Thus, it would be of great significance to apply reversible logic to designing secure cryptosystems. As far as is known, this is the first attempt to apply reversible logic to developing secure cryptosystems. In a prototype of a reversible ALU for a crypto-processor, reversible designs of adders and Montgomery multipliers are presented. The reversible designs of a carry propagate adder, four-to-two and fiveto-two carry save adders are presented using a reversible TSG gate. One of the important properties of the TSG gate is that it can work singly as a reversible full adder. In order to design the reversible Montgomery multiplier, novel reversible sequential circuits are also proposed which are integrated with the proposed adders to design a reversible modulo multiplier. It is intended that this paper will provide a starting point for developing cryptosystems secure against DPA attacks.

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“…Therefore, an efficient MMM architecture under limited hardware resources is important from a system performance point of view. Several MMM architectures have been proposed [3,4,5,6]. Although the processing element (PE) structure proposed in previous researches is adequate for designing a systolic multiplier, it is insufficient for obtaining optimality.…”

Section: Introductionmentioning

confidence: 99%

New systolic modular multiplication architecture for efficient Montgomery multiplication

Choi

Lee

2015

IEICE Electron. Express

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We propose a new low complexity Montgomery algorithm enabling the efficient selection of the quotient value necessary for an exact division in Montgomery multiplication. We also present two new systolic multipliers which use similar data flows as described in the most significant bit (MSB)-first GF(2 m ) multiplier in [1]. The proposed parallel and serial multipliers have less hardware and time complexities compared to related multiplier. The serial multiplier can be well applied to space-limited hardware. Furthermore, our proposed systolic multipliers include regularity, modularity, local interconnection, and unidirectional data flow features.

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Modified Montgomery modular multiplication and RSA exponentiation techniques

Cited by 125 publications

References 6 publications

Efficient Trapdoor-Based Client Puzzle Against DoS Attacks

Efficient Trapdoor-Based Client Puzzle Against DoS Attacks

Reversible Logic to Cryptographic Hardware: A New Paradigm

New systolic modular multiplication architecture for efficient Montgomery multiplication

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