Reversible Logic to Cryptographic Hardware: A New Paradigm

Thapliyal, Himanshu; Zwoliński, Mark

doi:10.1109/mwscas.2006.382067

Cited by 32 publications

(26 citation statements)

References 21 publications

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“…9 shows the proposed four-to-two reversible CSA. Table 1 shows that the proposed reversible CSA requires lower quantum cost than the existing one found in the literature [16] .…”

Section: Garbage Outputmentioning

confidence: 94%

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Efficient Reversible Montgomery Multiplier and Its Application to Hardware Cryptography

Nayeem¹

2009

J. of Computer Science

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Problem Statement: Arithmetic Logic Unit (ALU) of a crypto-processor and microchips leak information through power consumption. Although the cryptographic protocols are secured against mathematical attacks, the attackers can break the encryption by measuring the energy consumption. Approach: To thwart attacks, this study proposed the use of reversible logic for designing the ALU of a crypto-processor. Ideally, reversible circuits do not dissipate any energy. If reversible circuits are used, then the attacker would not be able to analyze the power consumption. In order to design the reversible ALU of a crypto-processor, reversible Carry Save Adder (CSA) using Modified TSG (MTSG) gates and architecture of Montgomery multiplier were proposed. For reversible implementation of Montgomery multiplier, efficient reversible multiplexers and sequential circuits such as reversible registers and shift registers were presented. Results: This study showed that modified designs perform better than the existing ones in terms of number of gates, number of garbage outputs and quantum cost. Lower bounds of the proposed designs were established by providing relevant theorems and lemmas. Conclusion: The application of reversible circuit is suitable to the field of hardware cryptography.

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“…9 shows the proposed four-to-two reversible CSA. Table 1 shows that the proposed reversible CSA requires lower quantum cost than the existing one found in the literature [16] .…”

Section: Garbage Outputmentioning

confidence: 94%

“…Proposed reversible register: Figure 10 shows the implementation of reversible clocked D flip-flop [16,17] . The reversible D flip-flops can be used to implement a reversible register.…”

Section: Garbage Outputmentioning

confidence: 99%

Efficient Reversible Montgomery Multiplier and Its Application to Hardware Cryptography

Nayeem¹

2009

J. of Computer Science

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“…Fig. 3a illustrates a reversible level sensitive D FlipFlop which implements the characteristics function of a latch [14] …”

Section: Definitionmentioning

confidence: 99%

“…Chang and Cheng tried to avoid the clock altogether with asynchronous self-timed synthesis techniques that were modified to produce reversible asynchronous sequential circuits [10]. At the same time, researchers started to report formulations for simple reversible clocked latches and flip flops elements [11,12,13,14]. Many additional proposals followed with more elaborated synchronous reversible designs for shift registers [15], counters [16], and even a reversible general information processing unit that included a cache subcircuit [17].…”

Section: Introductionmentioning

confidence: 99%

Using the Asynchronous Paradigm for Reversible Sequential Circuit Implementation

Feinstein¹,

Thornton

2012

2012 IEEE 42nd International Symposium on Multiple-Valued Logic

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“…Thus, any development in this domain can be directly applied to future technologies. Finally, the use of reversible circuits is already found in low power CMOS designs, adiabatic circuits [4,5], cryptography [6], optical computing [7] and digital signal processing [8,9] requiring that all the information encoded in the inputs be preserved in outputs.…”

Section: Introductionmentioning

confidence: 99%

Reversible Architecture of Computer Arithmetic

Sultana¹,

Radecka²

2014

IJCA

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Reversible logic plays an important role in emerging low power designs and quantum computing. This paper presents an efficient way to realize reversible arithmetic circuits especially targeting toward reversible arithmetic logic unit (RALU). In literature for reversible logic, not a significant advancement is found in integrating both logical and arithmetical functions, commonly known as arithmetic logic unit (ALU), a key feature of any computing system architecture. Here, this work presents a novel reversible arithmetic logic unit (ALU) performing basic functions similar to classical ALU such as addition, subtraction, AND, OR and XOR operations. Additional functions such as, NAND, NOR, XNOR and logical functions with single input inverted, overflow detection and comparison can also be performed with this design. The integration of these operations in single module using less number of control signals is not available in any of existing approaches. The design and analysis based on different parameters of reversible circuits -number of gates, garbage bits and quantum cost as well as simulation results are presented here. The proposed design offers efficient programmability and more flexibility than other methods. General TermsArithmetic design and logic structures.

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Reversible Logic to Cryptographic Hardware: A New Paradigm

Cited by 32 publications

References 21 publications

Efficient Reversible Montgomery Multiplier and Its Application to Hardware Cryptography

Efficient Reversible Montgomery Multiplier and Its Application to Hardware Cryptography

Using the Asynchronous Paradigm for Reversible Sequential Circuit Implementation

Reversible Architecture of Computer Arithmetic

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