Modified Hotspot Cache Architecture: A Low Energy Fast Cache for Embedded Processors

Abstract

The cache memory plays a crucial role in the performance of any processor. The cache memory (SRAM), especially the on chip cache, is 3-4 times faster than the main memory (DRAM). It can vastly improve the processor performance and speed. Also the cache consumes much less energy than the main memory. That leads to a huge power saving which is very important for embedded applications. In today's processors, although the cache memory reduces the energy consumption of the processor, however the energy consumption in the on-chip cache account to almost 40% of the total energy consumption of the processor. In this paper, we propose a cache architecture, for the instruction cache, that is a modification of the hotspot architecture. Our proposed architecture consists of a small filter cache in parallel with the hotspot cache, between the L1 cache and the main memory. The small filter cache is to hold the code that was not captured by the hotspot cache. We also propose a prediction mechanism to steer the memory access to either the hotspot cache, the filter cache, or the L1 cache. Our design has both a faster access time and less energy consumption compared to both the filter cache and the hotspot cache architectures. We use Mibench and Mediabench benchmarks, together with the simplescalar simulator in order to evaluate the performance of our proposed architecture and compares it with the filter cache and the hotspot cache architectures. The simulation results show that our design outperforms both the filter cache and the hotspot cache in both the average memory access time and the energy consumption.

Revisiting level-0 caches in embedded processors

“…Besides these designs, other designs also exploit a small L0 cache [24,3,11,4,7,9]. In the HotSpot cache [24] and its variant [3], the L0 cache is used in the I-cache to store "hot" loops which have high execution fraction, to reduce accesses to the L1 cache.…”

“…6. 3 In ARM Cortex-M3 [2], while the AGU does not take a whole stage, its clock speed is low, around 100MHz [20]). In this figure, the target architecture is the ARM11 processor [1].…”

“…In the HotSpot cache [24] and its variant [3], the L0 cache is used in the I-cache to store "hot" loops which have high execution fraction, to reduce accesses to the L1 cache. It does so by using the BTB to identify fetch addresses which belong to the hot loops.…”

A Survey of the Heterogeneous Computing Platform and Related Technologies

“…A research [14] point out that some frequently used data are not taken into hotspots cache, and hence they present a new cache framework that introduce hotspots cache and filter cache between L1 cache and memory at the same time. Their experiment shows the cache efficiency is improved.…”

Web Application’s Reliability Improvement Through Architectural Patterns

“…Cache [28] on and cache off are used to activate and deactivate caching. The system has three states namely normal state, SOS state and rescue state.…”