Modified Clipped LMS Algorithm

IEICE Electron. Express

2018

Motivated by reduction of computational complexity and improvement of convergence speed, this work develops a high-speed VLSI realization of the adaptive FIR filter based on the delayed dual sign LMS (DDSLMS) algorithm. Not only is the computation of the proposed algorithm the same as that of the sign LMS algorithm, but also the convergence characteristic is close to that of the LMS algorithm. The fine-grained dot-product unit and multiple-input-addition unit are adopted to reduce the latency of critical path. From the ASIC synthesis results we find that the proposed architecture of an 8-tap filter has nearly 38% less power and nearly 43% less area-delay-product (ADP) than the best existing structure.

Section: The Proposed Delayed Dual Sign Lms Algorithmmentioning

confidence: 99%

A high-speed realization of the delayed dual sign LMS algorithm

Wang

Zhao

IEICE Electron. Express

2018

“…The computation of SLMS algorithm is greatly reduced especially when eðnÞ is equal to zero, and at the same time this algorithm does not introduce any operations [12]. The prominent feature of SLMS algorithm is utilization of the quantization scheme to reduce the computation complexity.…”

Section: The Proposed Modified Sign-error Lms Algorithmmentioning

confidence: 99%

VLSI implementation of the modified sign-error LMS adaptive algorithm

Wang

IEICE Electron. Express

et al. 2017

Motivated by reduction of computational complexity, this work develops a delay-optimized VLSI architecture of the adaptive filter based on the modified sign-error LMS (MSLMS) algorithm. The proposed algorithm uses a three-level quantization strategy applied to the modified sign function containing a threshold parameter. The amount of computation of the proposed architecture is not only less than half of the traditional structure, but also the convergence characteristic is close to that of the LMS algorithm. The fine-grained dot-product unit and multiple-input-addition unit are adopted to reduce the latency of critical path. From the ASIC synthesis results we find that the proposed design for filter length 8-tap has roughly 31% less power and 53% less area-delay-product (ADP) than the best of existing structures.

EURASIP J. Adv. Signal Process.

“…An approximation of the NLMS similar to the clipped LMS algorithm [26][27][28] is proposed. This approach, termed low-complexity normalized LMS (LCNLMS), is suitable for efficient hardware implementation and maintains the fast convergence of the NLMS.…”

Section: Adaptation Of Complex-gain Lut Predistortersmentioning

confidence: 99%

“…Similarly to (27), the LCNLMS can also be applied to the linearly interpolated case, leading to the following update equations:…”

Section: Updating a Linearly-interpolated Lutmentioning

confidence: 99%

Efficient Lookup Table-Based Adaptive Baseband Predistortion Architecture for Memoryless Nonlinearity

Waheed

Zhou

2010

Digital predistortion is an effective means to compensate for the nonlinear effects of a memoryless system. In case of a cellular transmitter, a digital baseband predistorter can mitigate the undesirable nonlinear effects along the signal chain, particularly the nonlinear impairments in the radiofrequency (RF) amplifiers. To be practically feasible, the implementation complexity of the predistorter must be minimized so that it becomes a cost-effective solution for the resource-limited wireless handset. This paper proposes optimizations that facilitate the design of a low-cost high-performance adaptive digital baseband predistorter for memoryless systems. A comparative performance analysis of the amplitude and power lookup table (LUT) indexing schemes is presented. An optimized low-complexity amplitude approximation and its hardware synthesis results are also studied. An efficient LUT predistorter training algorithm that combines the fast convergence speed of the normalized least mean squares (NLMSs) with a small hardware footprint is proposed. Results of fixed-point simulations based on the measured nonlinear characteristics of an RF amplifier are presented.