Modified Booth Multipliers With a Regular Partial Product Array

Abstract

The conventional modified Booth encoding (MBE) generates an irregular partial product array because of the extra partial product bit at the least significant bit position of each partial product row. In this brief, a simple approach is proposed to generate a regular partial product array with fewer partial product rows and negligible overhead, thereby lowering the complexity of partial product reduction and reducing the area, delay, and power of MBE multipliers. The proposed approach can also be utilized to regularize the partial product array of posttruncated MBE multipliers. Implementation results demonstrate that the proposed MBE multipliers with a regular partial product array really achieve significant improvement in area, delay, and power consumption when compared with conventional MBE multipliers.

FPGA design, simulation and prototyping of a high speed 32-bit pipeline multiplier based on Vedic mathematics

“…In addition to this, he also used hybrid adders to perform fast summation in getting final product. Similar attempt was made by Shiann-Rong Kuang et al [5], who redesigned MBE, in order to eliminate the generation of an irregular partial product array. Their modifications have given a significant improvement in realizing a multiplier with less area, delay, and power [4,5].…”

“…Similar attempt was made by Shiann-Rong Kuang et al [5], who redesigned MBE, in order to eliminate the generation of an irregular partial product array. Their modifications have given a significant improvement in realizing a multiplier with less area, delay, and power [4,5]. Magnus Sjalander and Per Larsson-Edefors [6] have presented a twin precision algorithm to accelerate multiplication.…”

FPGA Implementation of Low Power Booth Multiplier Using Radix-4 Algorithm

“…As the applicationsof Array multipliers were introduced the clock rates increased as well as timing constrains became austere. Ever since then methods to implement multiplication are proposed which are more sophisticated [1][2][3][4]. As known the use of multiplication operation indigital computing and digital electronics is very intense especially in the field of multimedia and digital signal processing (DSP) applications [6].…”

Implementation of Modified Booth Encoding Multiplier for signed and unsigned 32 bit numbers

“…Among these three speeds is the one which requires special attention. If we observe closely multiplication operation involves two steps one is producing partial products and adding these partial products [3]. Thus, the speed of a multiplier hardly depends on how fast generate the partial products and how fast we can add them together.…”

“…To speed up the addition among the partial products we need fast adder architectures. Since the multipliers have a significant impact on the performance of the entire system, many high performance algorithms and architectures have been proposed [1][2][3][4][5][6][7][8][9][10][11][12]. The very high speed and dedicated multipliers are used in pipeline and vector computers.…”