Modification of the tunneling barrier in a nanocrystalline silicon single-electron transistor

Kamiya, Toshio; Tan, Yong Ren; Durrani, Z. A. K.; Ahmed, H.

doi:10.1016/s0022-3093(01)01180-2

Cited by 7 publications

(5 citation statements)

References 12 publications

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“…After defining the PC-Trs in the same manner, a multiple step oxidation process was applied, which was proposed to oxidize the a-Si:H selectively and to convert it to SiO x (x < 2) without increasing L grain [17,18]. This is low-temperature oxidation (650-750°C) followed by high-temperature (1000°C) annealing.…”

Section: Materials Optimisation Towards Room-temperature Nanosilicon Smentioning

confidence: 99%

Nanosilicon for single-electron devices

Mizuta

Furuta

Kamiya

et al. 2004

Current Applied Physics

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This paper presents a brief overview of the physics of nanosilicon materials for single-electron device applications. We study how a nanosilicon grain and a discrete grain boundary work as a charging island and a tunnel barrier by using a point-contact transistor, which features an extremely short and narrow channel. Single-electron charging phenomena are investigated by comparing asprepared devices and various oxidized devices. The optimization of grain and grain-boundary structural parameters is discussed for improving the Coulomb blockade characteristics and realizing room temperature device operation.

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Section: Materials Optimisation Towards Room-temperature Nanosilicon Smentioning

confidence: 99%

Nanosilicon for single-electron devices

Mizuta

Furuta

Kamiya

et al. 2004

Current Applied Physics

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“…The phosphorus concentration was measured to be 1.5Ϯ0.5ϫ10 19 cm Ϫ3 in both the asdeposited and passivated films. 13 However, in the confined NW channel, GBs can lie laterally across the NW, controlling the electrical characteristics of the NWs. The grain structure is visible and the grains are typically 20-30 nm wide.…”

Section: Methodsmentioning

confidence: 99%

Reduction of grain-boundary potential barrier height in polycrystalline silicon with hot H2O-vapor annealing probed using point-contact devices

Kamiya

Durrani

Ahmed

et al. 2003

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Anneal treatment to reduce the creation rate of light-induced metastable defects in device-quality hydrogenated amorphous silicon Appl. Phys. Lett. 98, 201908 (2011); 10.1063/1.3592264 Effects of grain boundaries on performance and hot-carrier reliability of excimer-laser annealed polycrystalline silicon thin film transistors Optical absorption and Hall effect in (220) and (400) oriented polycrystalline silicon filmsThe effects of hot H 2 O-vapor annealing were investigated on local carrier transport properties over a few grain boundaries in polycrystalline silicon. It shows that hot H 2 O-vapor annealing effectively reduces grain-boundary dangling bonds and the potential barrier height. In addition, it narrows the distribution of the barrier height value significantly. These effects are thought to originate from oxidation in the vicinity of the film surface, and from hydrogenation in the deeper region. Our results suggest that H 2 O annealing can improve the carrier transport properties by opening up shorter percolation paths and by increasing the effective carrier mobility and density.

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“…The multi-step oxidation process was proposed in order to oxidize the aSi:H selectively and to convert it to SiO x (x 2) without increasing L grain [28] [29]. It was found from SIMS depth profile of oxygen concentration [29] that the low temperature oxidation step oxidizes the GBs selectively and the subsequent high-temperature annealing increases qV B and R t of the GBs. Also, encapsulation of the grains with the silicon oxide may prevent any grain growth during high-temperature annealing.…”

Section: Optimisation Of Grain and Grain Boundaries Towards Room-tempmentioning

confidence: 99%

“…The SIMS depth profiles of oxygen concentration are shown in Fig. 12 for the as-deposited and multi-step oxidized nc-Si:H films [29]. These results show that the minimum oxygen concentration at the bottom of the 20-nm-thick nc-Si:H film is about 2x10 21 cm -3 , so that the value of x in a-SiO x is estimated to be only about 0.13, assuming that the a-Si:H phases with a volume fraction of 30% were oxidized.…”

Section: Ep Epmentioning

confidence: 99%

“…These results show that the minimum oxygen concentration at the bottom of the 20-nm-thick nc-Si:H film is about 2x10 21 cm -3 , so that the value of x in a-SiO x is estimated to be only about 0.13, assuming that the a-Si:H phases with a volume fraction of 30% were oxidized. If we assume that oxidation also proceeds from both sidewalls and the oxygen concentration is simply given by an addition law, the minimum oxygen concentration at the center of the channel would be 1x10 22 cm -3 , corresponding to x = 0.67 [29]. As W is increased, this value decreases gradually, resulting in a lower tunnel barrier at the center of the channel.…”

Section: Ep Epmentioning

confidence: 99%

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Single-Electron Charging Phenomena in Nano/Polycrystalline Silicon Point Contact Transistors

Mizuta

Furuta²,

Kamiya³

et al. 2003

SSP

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Abstract. This paper gives a review of our recent work investigating the physics of single-electron charging phenomena in nano/polycrystalline silicon nanostructures. We first provide a short overview on the research of silicon-based single-electron devices from the last decade. Various single-electron transistor structures are compared in terms of control of electron islands and tunnel barriers. We then study the single-electron charging phenomena in nano/polycrystalline silicon nanostructures. A novel point-contact transistor is introduced, which features an extremely short and narrow nano/poly-Si nanowire as the transistor's channel. This structure is suitable for studying how a grain smaller than 10 nm in size and a discrete grain boundary work as a charging island and a tunnel barrier, respectively. The relationships between structural and electrical parameters of grains/grain-boundaries and the resulting Coulomb blockade characteristics for the point contact transistors are investigated by applying various passivation processes. Finally, optimisation of grain and grain-boundary structures is discussed for improving the Coulomb blockade characteristics and realizing nano/poly-Si single-electron transistors operating at room temperature.

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Modification of the tunneling barrier in a nanocrystalline silicon single-electron transistor

Cited by 7 publications

References 12 publications

Nanosilicon for single-electron devices

Nanosilicon for single-electron devices

Reduction of grain-boundary potential barrier height in polycrystalline silicon with hot H2O-vapor annealing probed using point-contact devices

Single-Electron Charging Phenomena in Nano/Polycrystalline Silicon Point Contact Transistors

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