2014
DOI: 10.1039/c4ra08548e
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Modification of a polymer gate insulator by zirconium oxide doping for low temperature, high performance indium zinc oxide transistors

Abstract: Indium zinc oxide (IZO) thin film transistors (TFTs) with poly(4-vinylphenol-co-methylmethacrylate) (PVPco-PMMA) gate insulators were fabricated at a low temperature (250 C). The bottom gate IZO TFTs with a PVP-co-PMMA gate electric film exhibited inferior device performance to the top gate IZO TFTs, which was attributed to sputtering damage of the underlying polymer gate dielectric film during IZO channel formation. The charge carrier transport and interface properties of the IZO TFTs could be further improve… Show more

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Cited by 25 publications
(17 citation statements)
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“…Hereafter, the TFTs fabricated at OPP1 condition were utilized for further bending studies. Considering the plasma-induced thermal damage on the organic dielectric layer, our hysteresis value is much lower than that (~10 V) from the IZO/ PVA-co-PMMA bottom-gated transistors18.…”
Section: Resultsmentioning
confidence: 67%
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“…Hereafter, the TFTs fabricated at OPP1 condition were utilized for further bending studies. Considering the plasma-induced thermal damage on the organic dielectric layer, our hysteresis value is much lower than that (~10 V) from the IZO/ PVA-co-PMMA bottom-gated transistors18.…”
Section: Resultsmentioning
confidence: 67%
“…The carrier concentration of the sputtered IGZO channel can be modified by controlling the argon (Ar) and oxygen (O 2 ) gas flow rate ratio during sputtering422. However, sputtering can incur plasma-induced thermal damage on the underlying organic dielectric layer1824. In our preliminary experiment, unwanted wrinkles and roughness on the PMMA dielectric layer was generated during sputtering (supporting information (SI), S1).…”
mentioning
confidence: 98%
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“…The electrical response of the hybrid dielectric gate-based TFT devices was analyzed from drain–source current ( I ds ) versus drain–source voltage ( V ds ) curves, measured at different gate–source voltages ( V gs ) (family curves) and drain–source current ( I ds ) versus gate–source voltage curves, measured at fixed V ds (transfer characteristics). The latter measurements were fit to following eq 1(22,23) to determine the channel mobility, μ sat , and threshold voltage, V t , parameters of the deviceswhere W and L are the width and length of the channel and C H is the capacitance per unit area of the PMMA–ZrO 2 hybrid dielectric gate layer.…”
Section: Resultsmentioning
confidence: 99%
“…The smooth surface ensures reduced electron scattering at the channel/dielectric interface, 20 whereas the high oxidation state leads to a reduction in electron trap sites 21 due to the fact that hydroxyl groups created by imperfect dehydroxylation are typically quite prominent electron trap sites. In the case of SiO 2 , this electron trapping mechanism is believed to involve the following reactions: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 25 However, even though these studies succeeded in producing metal oxide TFTs with inorganic/organic bilayer or hybrid gate dielectrics, they relied on using rigid substrates. Furthermore, there has to date been only very few studies into the bending characteristics of flexible TFTs.…”
Section: Introductionmentioning
confidence: 98%